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參數(shù)資料
| 型號： | AT17LV010A |
| 廠商： | Atmel Corp. |
| 英文描述： | 1M FPGA Configuration EEPROM Memory(1M 現(xiàn)場可編程門陣列（FPGA）配置EEPROM存儲器) |
| 中文描述： | 100萬FPGA配置存儲器（100萬現(xiàn)場可編程門陣列（FPGA）的配置的EEPROM存儲器） |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 205K |
| 代理商： | AT17LV010A |
AT17C/LV512A/010A
2
Block Diagram
Device Configuration
The control signals for the configuration EEPROM–nCS,
OE, and DCLK–interface directly with the FPGA device
control signals. All FPGA devices can control the entire
configuration process and retrieve data from the configura-
tion EEPROM without requiring an external intelligent
controller.
The configuration EEPROM’s OE and nCS pins control the
tri-state buffer on the DATA output pin and enable the
address counter and the oscillator. When OE is driven Low,
the configuration EEPROM resets its address counter and
tri-states its DATA pin. The nCS pin also controls the out-
put of the AT17A Series Configurator. If nCS is held High
after the OE reset pulse, the counter is disabled and the
DATA output pin is tri-stated. When nCS is driven Low, the
counter and the DATA output pin are enabled. When OE is
driven Low again, the address counter is reset and
the DATA output pin is tri-stated, regardless of the state
of the nCS.
When the Configurator has driven out all of its data and
nCASC is driven Low, the device tri-states the DATA pin to
avoid contention with other Configurators. Upon power-up,
the address counter is automatically reset.
The READY pin is available as an open-collector indicator
of the device’s reset status; it is driven Low while the device
is in its power-on reset cycle and released (tri-stated) when
the cycle is complete.
This document discusses the EPF10K device interface.
For more details or information on other Altera applications,
please reference the “AT17A Series Conversions from
Altera FPGA Serial Configuration Memories” application
note.
EEPROM
CELL
MATRIX
ROW
DECODER
COLUMN
DECODER
TC
nCS
DCLK READY
OE
nCASC (A2)
DATA
BIT
COUNTER
OSC
OSC
CONTROL
PROGRAMMING
DATA SHIFT
REGISTER
PROGRAMMING
MODE LOGIC
ROW
ADDRESS
COUNTER
POWER ON
RESET
SER_EN
WP1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17C010 | 1M FPGA Configuration EEPROM Memory(1M 現(xiàn)場可編程（FPGA）配置EEPROM存儲器) |
| AT17C020A | FPGA Configuration EEPROM Memory |
| AT17C002A-10JC | FPGA Configuration EEPROM Memory |
| AT17LV020A | FPGA Configuration EEPROM Memory |
| AT17LV512A | FPGA Configuration EEPROM Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV010A-10BJC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A-10BJI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A-10CC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A-10CI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A10JC | 制造商:Atmel Corporation 功能描述: |
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