參數(shù)資料
型號: AT17LV010A
廠商: Atmel Corp.
英文描述: 1M FPGA Configuration EEPROM Memory(1M 現(xiàn)場可編程門陣列(FPGA)配置EEPROM存儲器)
中文描述: 100萬FPGA配置存儲器(100萬現(xiàn)場可編程門陣列(FPGA)的配置的EEPROM存儲器)
文件頁數(shù): 4/13頁
文件大?。?/td> 205K
代理商: AT17LV010A
AT17C/LV512A/010A
4
Figure 2.
Configuration with Multiple AT17A Series Configurators
Notes:
1. 1.0 k
resistors used unless otherwise specified.
2. Use of the READY pin is optional.
3. Introducing a RC delay to the input of nCONFIG is recommended to ensure that VCC (5V/3.3V) is reached before
configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)
4. Reset polarity of EEPROM must be set active Low (OE active High).
AT17A Series Reset Polarity
The AT17A Series Configurator allows the user to program
the reset polarity as either RESET/OE or RESET/OE. For
more details, please reference the “Programming Specifi-
cation for Atmel’s FPGA Configuration EEPROMs”
application note.
Programming Mode
The programming mode is entered by bringing SER_EN
Low. In this mode the chip can be programmed by the
2-wire serial interface. The programming is done at VCC
supply only. Programming super voltages are generated
inside the chip. See the “Programming Specification for
Atmel’s Configuration EEPROMs” application note for fur-
ther information. The AT17 A-series parts are read/write at
5V nominal. The AT17LV A-series parts are read/write at
3.3V nominal.
Standby Mode
The AT17A Series Configurator enters a low-power
standby mode whenever nCS is asserted High. In this
mode, the configuration consumes less than 0.5 mA of cur-
rent at 5V. The output remains in a high-impedance state
regardless of the state of the OE input.
MSEL1
nSTATUS
MSEL0
CONF_DONE
DATA0
DCLK
nCONFIG
EPF10K
AT17C512A/010A
AT17LV512A/010A
DEVICE 1
GND
VCC
VCC
OE
nCS
nCASC
DATA
DCLK
AT17C512A/010A
AT17LV512A/010A
DEVICE 2
OE
nCS
DATA
DCLK
VCC
READY
READY
nCE
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參數(shù)描述
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