- 您現(xiàn)在的位置：買賣IC網 > PDF目錄381377 > ASM5I9773AG-52-ER (ALLIANCE SEMICONDUCTOR CORP) Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85 PDF資料下載
參數(shù)資料
| 型號： | ASM5I9773AG-52-ER |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85 |
| 中文描述： | 9773 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 1 MM HEIGHT, GREEN, TQFP-52 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 624K |
| 代理商： | ASM5I9773AG-52-ER |
June 2005
rev 0. 3
AC Electrical Specifications
(VDD = 2.5V ±5%, T
A
= –40°C to +85°C)
7
Parameter
Description
f
VCO
VCO Frequency
ASM5I9773A
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
7 of 16
Notice: The information in this document is subject to change without notice.
Condition
Min
200
Typ
-
Max
380
Unit
MHz
÷4 Feedback
50
-
95
÷6 Feedback
33.3
-
63.3
÷8 Feedback
25
-
47.5
÷10 Feedback
20
-
38
÷12 Feedback
16.6
-
31.6
÷16 Feedback
12.5
-
23.75
÷20 Feedback
10
-
19
÷24 Feedback
8.3
-
15.8
÷32 Feedback
6.25
-
11.8
÷40 Feedback
5
-
9.5
f
in
Input Frequency
Bypass mode (PLL_EN = 0)
0
-
200
MHz
f
refDC
V
PP
V
CMR
t
r
, t
f
Input Duty Cycle
Peak-Peak Input Voltage
Common Mode Range
8
LVPECL
LVPECL
25
500
1.2
-
-
-
75
1000
VDD– 0.6
%
mV
V
TCLK Input Rise/FallTime
0.7V to 1.7V
-
-
1.0
nS
÷2 Output
100
-
190
÷4 Output
50
-
95
÷6 Output
33.3
-
63.3
÷8 Output
25
-
47.5
÷10 Output
20
-
38
÷12 Output
16.6
-
31.6
÷16 Output
12.5
-
23.75
÷20 Output
10
-
19
f
MAX
Maximum Output Frequency
÷24 Output
8.3
-
15.8
MHz
f
SCLK
Serial Clock Frequency
-
-
20
MHz
f
MAX
< 100 MHz
f
MAX
> 100 MHz
0.6V to 1.8V
47.5
-
52.5
DC
Output Duty Cycle
45
-
55
%
t
r
, t
f
Output Rise/Fall times
0.1
-
1.0
nS
TCLK to FB_IN
-125
-
125
t
(
φ
)
Propagation Delay
(static phase offset)
PCLK to FB_IN
-125
-
125
pS
Notes:
7. AC characteristics apply for parallel output termination of 50
to V
TT
. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed
by characterization and are not 100% tested.
8. V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
range and the input swing
lies within the V
PP
(AC) specification. Violation of VCMR or VPP impacts static phase offset t
(
φ
)
.
相關PDF資料 |
PDF描述 |
|---|---|
| ASM5I9773AG-52-ET | Octal D-Type Flip-Flops With Clear 20-SO -40 to 85 |
| ASM5I9774AG-52-ER | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774AG-52-ET | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A | Octal D-Type Flip-Flops With Clear 20-SO -40 to 85 |
| ASM5I9774A-52-ER | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9773AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
發(fā)布緊急采購，3分鐘左右您將得到回復。