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參數(shù)資料
| 型號： | ASM5I9773AG-52-ER |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85 |
| 中文描述： | 9773 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 1 MM HEIGHT, GREEN, TQFP-52 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 624K |
| 代理商： | ASM5I9773AG-52-ER |
June 2005
rev 0. 3
‘SpreadTrak’
ASM5I9773A
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
4 of 16
Notice: The information in this document is subject to change without notice.
Many systems being designed now utilize a technology
called Spread Spectrum Frequency Timing Generation.
ASM5I9773A is designed so as not to filter off the Spread
Spectrum feature of the Reference Input, assuming it
exists.
When a zero delay buffer is not designed to pass the
Spread Spectrum feature through, the result is a
significant amount of tracking skew which may cause
problems in the systems requiring synchronization.
Table 1: Frequency Table
Feedback
Output Divider
÷4
VCO
Input Frequency Range
(AVDD = 3.3V)
50 MHz to 125 MHz
Input Frequency Range
(AVDD = 2.5V)
50 MHz to 95 MHz
Input Clock * 4
÷6
Input Clock * 6
33.3 MHz to 83.3 MHz
33.3 MHz to 63.3 MHz
÷8.
Input Clock * 8
25 MHz to 62.5 MHz
25 MHz to 47.5 MHz
÷10
Input Clock * 10
20 MHz to 50 MHz
20 MHz to 38 MHz
÷12
Input Clock * 12
16.6 MHz to 41.6 MHz
16.6 MHz to 31.6 MHz
÷16
Input Clock * 16
12.5 MHz to 31.25 MHz
12.5 MHz to 23.75 MHz
÷20
Input Clock * 20
10 MHz to 25 MHz
10 MHz to19 MHz
÷24
Input Clock * 24
8.3 MHz to 20.8 MHz
8.3 MHz to 15.8 MHz
÷32
Input Clock * 32
6.25 MHz to 15.625 MHz
6.25 MHz to 11.8 MHz
÷40
Input Clock * 40
5 MHz to 12.5 MHz
5 MHz to 9.5 MHz
Table 2. Function Table (Configuration Controls)
Control
Default
REF_SEL
1
TCLK0, TCLK1
0
1
PECL_CLK
TCLK_SEL
1
TCLK0
TCLK1
VCO÷1
(high input frequency range)
PLL enabled. The VCO output
connects to the output dividers
QC2 and QC3 are inverted
(180° phase shift) with respect to
QC0 and QC1
VCO_SEL
1
VCO÷2 (low input frequency range)
PLL_EN
1
Bypass mode, PLL disabled. The input clock connects to
the output dividers
INV_CLK
1
QC2 and QC3 are in phase with QC0 and QC1
MR#/OE
1
Outputs disabled (three-state) and reset of the device.
During reset/output disable the PLL feedback loop is open
and the VCO running at its minimum frequency. The device
is reset by the internal power-on reset (POR) circuitry
during power-up.
Outputs enabled
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9773AG-52-ET | Octal D-Type Flip-Flops With Clear 20-SO -40 to 85 |
| ASM5I9774AG-52-ER | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774AG-52-ET | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A | Octal D-Type Flip-Flops With Clear 20-SO -40 to 85 |
| ASM5I9774A-52-ER | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9773AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
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