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參數(shù)資料
| 型號(hào)： | ASM5I9773AG-52-ER |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85 |
| 中文描述： | 9773 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 1 MM HEIGHT, GREEN, TQFP-52 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 624K |
| 代理商： | ASM5I9773AG-52-ER |
June 2005
rev 0. 3
DC Electrical Specifications
(VDD = 2.5V ± 5%, T
A
= – 40°C to + 85°C
)
Parameter
Description
V
IL
Input Voltage, Low
V
IH
Input Voltage, High
V
PP
Peak-Peak Input Voltage
V
CMR
Common Mode Range
4
V
OL
Output Voltage, Low
5
V
OH
Output Voltage, High
5
I
IL
Input Current, Low
5
I
IH
I
DDA
PLL Supply Current
I
DDQ
Quiescent Supply Current
I
DD
Dynamic Supply Current
C
IN
Input Pin Capacitance
Z
OUT
Output Impedance
DC Electrical Specifications
(VDD = 3.3V ± 5%, T
A
= – 40°C to + 85°C)
Parameter
Description
V
IL
Input Voltage, Low
V
IH
Input Voltage, High
V
PP
Peak-Peak Input Voltage
V
CMR
Common Mode Range
4
ASM5I9773A
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
6 of 16
Notice: The information in this document is subject to change without notice.
Condition
Min
-
1.7
Typ
-
Max
0.7
Unit
V
LVCMOS
LVCMOS
-
-
-
-
-
-
-
5
VDD+0.3
1000
VDD – 0.6
0.6
-
-100
100
V
LVPECL
LVPECL
I
OL
= 15 mA
I
OH
= –15 mA
VI
L
= VSS
V
IL
= VDD
AVDD only
250
1.0
-
1.8
-
-
mV
V
V
V
μA
μA
Input Current, High
6
-
10
mA
All VDD
pins except AVDD
Outputs loaded @ 100 MHz
-
-
8
mA
-
135
-
mA
-
14
4
-
22
pF
18
Condition
Min
-
Typ
-
Max
0.8
Unit
V
LVCMOS
LVCMOS
LVPECL
LVPECL
I
OL
= 24 mA
I
OL
= 12 mA
I
OH
= –24 mA
V
IL
= VSS
2.0
250
1.0
-
-
2.4
-
-
-
-
-
-
-
-
VDD+0.3
1000
VDD– 0.6
0.55
0.30
-
-100
V
mV
V
V
OL
Output Voltage, Low
5
V
V
OH
I
IL
Output Voltage, High
5
Input Current, Low
6
Input Current, High
6
V
μA
I
IH
V
IL
= VDD
-
-
100
μA
I
DDA
I
DDQ
I
DD
C
IN
Z
OUT
Notes:
4. V
CMR
(DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the V
CMR
range and the input
swing is within the V
PP
(DC) specification.
5. Driving one 50
parallel terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50
series terminated
transmission lines.
6. Inputs have pull-up or pull-down resistors that affect the input current.
PLL Supply Current
AVDD only
-
5
10
mA
Quiescent Supply Current
All VDD pins except AVDD
-
-
8
mA
Dynamic Supply Current
Outputs loaded @ 100 MHz
-
225
-
mA
Input Pin Capacitance
-
4
-
pF
Output Impedance
12
15
18
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9773AG-52-ET | Octal D-Type Flip-Flops With Clear 20-SO -40 to 85 |
| ASM5I9774AG-52-ER | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774AG-52-ET | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A | Octal D-Type Flip-Flops With Clear 20-SO -40 to 85 |
| ASM5I9774A-52-ER | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9773AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
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