參數(shù)資料
型號： ASM5I9773AG-52-ER
廠商： ALLIANCE SEMICONDUCTOR CORP
元件分類： 時鐘及定時
英文描述： Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85
中文描述： 9773 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
封裝： 1 MM HEIGHT, GREEN, TQFP-52
文件頁數(shù)： 3/16頁
文件大?。?/td> 624K
代理商： ASM5I9773AG-52-ER
June 2005
rev 0. 3
Pin Configuration
1
Pin
11
ASM5I9773A
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
3 of 16
Notice: The information in this document is subject to change without notice.
Name
PECL_CLK
I/O
I, PU
Type
LVPECL
LVPECL reference clock input
.
Description
12
PECL_CLK#
I
LVPECL
LVPECL reference clock input
.
9
TCLK0
I, PU
LVCMOS
LVCMOS/LVTTL reference clock input
.
10
TCLK1
I, PU
LVCMOS
LVCMOS/LVTTL reference clock input
.
44,46,48,50
QA(3:0)
O
LVCMOS
Clock output bank A
.
32,34,36,38
QB(3:0)
O
LVCMOS
Clock output bank B
.
16,18,21,23
QC(3:0)
O
LVCMOS
Clock output bank C
.
29
FB_OUT
O
LVCMOS
Feedback clock output
. Connect to FB_IN for normal operation.
Feedback clock input
. Connect to FB_OUT for normal operation. This
input should be at the same voltage rail as input reference clock.
See
Table 1. Frequency Table
.
LVCMOS
Synchronous pulse output
. This output is used for system
synchronization.
LVCMOS
PLL enable/bypass input
. When Low, PLL is disabled/bypassed and
the input clock connects to the output dividers.
LVCMOS
Master reset and Output enable/disable input
.
See
Table 2. Function Table (Configuration Controls)
.
LVCMOS
LVCMOS Clock reference select input
.
See
Table 2. Function Table (Configuration Controls)
.
LVCMOS
LVCMOS/LVPECL Reference select input
.
See
Table 2. Function Table (Configuration Controls)
.
LVCMOS
VCO Operating frequency select input
.
See
Table 2. Function Table (Configuration Controls)
.
LVCMOS
QC(2,3) Phase selection input
.
See
Table 2. Function Table (Configuration Controls)
.
LVCMOS
Feedback divider select input
. See
Table 6
.
LVCMOS
Frequency select input, Bank A
.
See
Table 3. Function Table (Bank A)
.
LVCMOS
Frequency select input, Bank B
.
See
Table 4. Function Table (Bank B)
.
LVCMOS
Frequency select input, Bank C
.
See
Table 5. Function Table (Bank C)
.
LVCMOS
Serial clock input
.
31
FB_IN
I, PU
LVCMOS
25
SYNC
O
6
PLL_EN
I, PU
2
MR#/OE
I, PU
8
TCLK_SEL
I, PU
7
REF_SEL
I, PU
52
VCO_SEL
I, PU
14
INV_CLK
I, PU
5,26,27
FB_SEL(2:0)
I, PU
42,43
SELA(1,0)
I, PU
40,41
SELB(1,0)
I, PU
19,20
SELC(1,0)
I, PU
3
SCLK
I, PU
4
SDATA
I, PU
LVCMOS
Serial data input
.
2.5V or 3.3V Power supply for bank A output clocks
2,3
.
2.5V or 3.3V Power supply for bank B output clocks
2,3
.
2.5V or 3.3V Power supply for bank C output clocks
2,3
.
2.5V or 3.3V Power supply for PLL
2,3
.
2.5V or 3.3V Power supply for core and inputs
2,3
.
45,49
VDDQA
Supply
VDD
33,37
VDDQB
Supply
VDD
22,17
VDDQC
Supply
VDD
13
AVDD
Supply
VDD
28
VDD
Supply
VDD
1
AVSS
Supply
Ground
Analog Ground
.
15,24,30,35,
39,47,51
Notes:
1. PU = Internal pull up, PD = Internal pull down.
2. A 0.1μF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins.
VSS
Supply
Ground
Common Ground
.
相關(guān)PDF資料
PDF描述
ASM5I9773AG-52-ET Octal D-Type Flip-Flops With Clear 20-SO -40 to 85
ASM5I9774AG-52-ER 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
ASM5I9774AG-52-ET 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
ASM5I9774A Octal D-Type Flip-Flops With Clear 20-SO -40 to 85
ASM5I9774A-52-ER Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ASM5I9773AG-52-ET 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
ASM5I9774A 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
ASM5I9774A-52-ER 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
ASM5I9774A-52-ET 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
ASM5I9774AG-52-ER 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
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