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參數(shù)資料
| 型號： | ASM5I9773AG-52-ER |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85 |
| 中文描述： | 9773 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 1 MM HEIGHT, GREEN, TQFP-52 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 624K |
| 代理商： | ASM5I9773AG-52-ER |
June 2005
rev 0. 3
AC Electrical Specifications
(VDD = 3.3V ±5%, T
A
= –40°C to +85°C)
11
Parameter
Description
ASM5I9773A
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
10 of 16
Notice: The information in this document is subject to change without notice.
Condition
Min
100
Typ
-
Max
200
Unit
÷2 Output
÷4 Output
50
-
125
÷6 Output
33.3
-
83.3
÷8 Output
25
-
62.5
MHz
÷10 Output
20
-
50
÷12 Output
16.6
-
41.6
÷16 Output
12.5
-
31.25
÷20 Output
10
-
25
f
MAX
Maximum Output Frequency
÷24 Output
8.3
-
20.8
MHz
f
SCLK
Serial Clock Frequency
-
-
20
MHz
f
MAX
< 100 MHz
f
MAX
> 100 MHz
0.55V to 2.4V
TCLK to FB_IN,
same VDD
PCLK to FB_IN,
same VDD
Skew within Bank A
48
-
52
DC
Output Duty Cycle
45
-
55
%
t
r
, t
f
Output Rise/Fall times
0.1
-
1.0
nS
-125
-
125
t(
φ
)
Propagation Delay
(static phase offset)
-125
-
125
pS
-
-
75
Skew within Bank B
-
-
100
t
sk(O)
Output-to-Output Skew
Skew within Bank C
-
-
150
pS
t
sk(B)
t
PLZ, HZ
t
PZL, ZH
Bank-to-Bank Skew
-
-
325
pS
Output Disable Time
-
-
8
nS
Output Enable Time
-
-
8
nS
÷4 Feedback
-
1.3–2.0
-
÷6 Feedback
-
0.7–1.3
-
÷8 Feedback
-
0.9–1.3
-
÷10 Feedback
-
0.6–1.1
-
÷12 Feedback
-
0.6–0.9
-
÷16 Feedback
-
0.4–0.6
-
BW
PLL Closed Loop Bandwidth (–3 dB)
÷20 Feedback
-
0.6–0.9
-
MHz
Same frequency
(125 MHz) RMS (1
σ
)
-
7
30
Same frequency
-
-
100
t
JIT(CC)
Cycle-to-Cycle Jitter
Multiple frequencies
Same frequency
(125 MHz) RMS (1
σ
)
-
-
375
pS
-
6
30
Same frequency
-
45
75
t
JIT(PER)
Period Jitter
Multiple frequencies
-
-
225
pS
t
JIT(
φ
)
t
LOCK
I/O Phase Jitter
I/O same VDD
-
-
150
pS
Maximum PLL Lock Time
-
-
1
mS
Notes:
11. AC characteristics apply for parallel output termination of 50
to V
TT
. Outputs are at same supply voltage unless otherwise stated. Parameters are
guaranteed by characterization and are not 100% tested.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9773AG-52-ET | Octal D-Type Flip-Flops With Clear 20-SO -40 to 85 |
| ASM5I9774AG-52-ER | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774AG-52-ET | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A | Octal D-Type Flip-Flops With Clear 20-SO -40 to 85 |
| ASM5I9774A-52-ER | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9773AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
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