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參數(shù)資料
| 型號(hào)： | ASM5I9773AG-52-ER |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85 |
| 中文描述： | 9773 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 1 MM HEIGHT, GREEN, TQFP-52 |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 624K |
| 代理商： | ASM5I9773AG-52-ER |
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June 2005
rev 0. 3
Power Management
The individual output enable/freeze control of the
ASM5I9773A allows the user to implement unique power
management schemes into the design. The outputs are
stopped in the logic ‘0’ state when the freeze control bits
are activated. The serial input register contains one
programmable freeze enable bit for 12 of the 14 output
clocks. The QC0 and FB_OUT outputs can not be frozen
with the serial port, this avoids any potential lock up
situation, should an error occur in the loading of the serial
ASM5I9773A
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
12 of 16
Notice: The information in this document is subject to change without notice.
data. An output is frozen when a logic ‘0’ is programmed
and enabled when a logic ‘1’ is written. The enabling and
freezing of individual outputs is done in such a manner as
to eliminate the possibility of partial “runt” clocks. The
serial input register is programmed through the SDATA
input by writing a logic ‘0’ start bit followed by 12 NRZ
freeze enable bits. The period of each SDATA bit equals
the period of the free running SCLK signal. The SDATA is
sampled on the rising edge of SCLK.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9773AG-52-ET | Octal D-Type Flip-Flops With Clear 20-SO -40 to 85 |
| ASM5I9774AG-52-ER | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774AG-52-ET | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A | Octal D-Type Flip-Flops With Clear 20-SO -40 to 85 |
| ASM5I9774A-52-ER | Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9773AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9774AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
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