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參數(shù)資料
| 型號(hào)： | ASCELL3912 |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | ER 10C 10#16 SKT RECP LINE |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO20 |
| 封裝： | TSSOP-20 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 122K |
| 代理商： | ASCELL3912 |
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell – Preliminary Data Sheet
ASCell3912
Rev. A, February 2000
Page 8 of 14
Austria Mikro Systeme International AG
1.2.6 Timing Diagrams
The following Figure 3 shows the timing for the write operation into the configuration register.
First the opcode is transmitted and it is followed by 9 instruction bits.
1
FB1
LNA
STR0
D_CLK
DATA
0
D_EN
STR5
FB0
t
Figure 3:
Write timing for the configuration register..
The following Figure 4 shows the timing of a read operation from the status register. After writing
the operation code to the ASCell3912, the ASCell3912 stays in high impedance state for one
more clock cycle and starts transmission of the selected bit sequence after that period.
RX
RQ1
RQ0
D_CLK
DATA
1
D_EN
0
gap=1
DR
μC
SC3912
t
Figure 4:
Read timing for status register.
In the following Figure 5 shows read out of the received data. In the example `Bx-bz` stands for
bit ′z′ of Byte ′y′, so B7-b5 depicts bit 5 of byte 7.
B15-b6
B15-b7
B0-b1
D_CLK
DATA
1
D_EN
1
gap=1
B0-b0
μC
SC3912
t
Figure 5:
Read out timing for received data (16 Bytes).
1.2.7 Interrupt and Wake-Up Pins
To provide the micro controller with time-critical information the receive/end transmission inter-
rupt (RE_INT) line is used. Figure 2 shows the timing of the RE_INT and WAKE_UP signals
during the reception. A high pulse is issued on this line, when one of the both conditions appear:
The reception of data is completed for the first time after a receiver wake-up.
The transmission of data has stopped. This interrupt is necessary status oriented CMT for
comfort orientated central locking functions (like window closing).
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