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參數(shù)資料
| 型號(hào)： | ASCELL3912 |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | ER 10C 10#16 SKT RECP LINE |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO20 |
| 封裝： | TSSOP-20 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 122K |
| 代理商： | ASCELL3912 |
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell – Preliminary Data Sheet
ASCell3912
Rev. A, February 2000
Page 12 of 14
Austria Mikro Systeme International AG
Pin
Name
Type
Description
17
D_EN
O
Enable data bus
18
D_CLK
I
Clock for serial interface
19
DATA
I/O
Data Input / Output for serial interface
20
DVDD
P
Digital positive supply
4
Application Schematic
DC to 100 kHz
RF_LO = f
R F
G. Schultes, ISM868_RX
Revision: 0, 99 07 16
f/64
+/-45°
Protocol
Decoder
Receiver
Timing
90°
Baseband
rators
Switchable
BFilters
Demodulator,
Sync
Data
Loop-filter
Divider
XTAL+
XTAL-
Phase Detector
O XTAL
O Local
DQuadrature
RE_INT
DATA
D_EN
D_CLK
WAKEUP
μC_CLK
DVCC
DGND
TEST
f =868.300 MHz
R F
Pre Filter
IRF
QDC
2*BBF
2*BBA
2*CMP
XTO
VCO
LPF
DIV PHD
2*ACC
DEM
AFC
LNA
DC-0
Bandwidth
Clock
AGND
AGND
AVDD
AVDD
LC-
GMC
Preamp.
PRA
RFGND
RF+
LC+
RF-
DVCC
DGND
ImExample
Optional
Figure 6: Basic application schematic of the ASCell3912.
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