參數(shù)資料
型號: ASCELL3912
廠商: AUSTRIAMICROSYSTEMS AG
元件分類: 通信及網(wǎng)絡
英文描述: ER 10C 10#16 SKT RECP LINE
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO20
封裝: TSSOP-20
文件頁數(shù): 3/14頁
文件大?。?/td> 122K
代理商: ASCELL3912
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell – Preliminary Data Sheet
ASCell3912
Rev. A, February 2000
Page 3 of 14
Austria Mikro Systeme International AG
TSSOP-20
D_EN
17
WAKEUP
RE_INT
μC_CLK
16
15
14
TEST2
TEST1
DGND
13
12
11
D_CLK
18
DATA
19
DVDD
20
RF+
1
RF-
LC+
LC-
2
3
4
XTAL+
XTAL-
AVDD
5
6
7
AGND
GMC
RFGND
8
9
10
This pin-out is preliminary and will change for the real implementation!
This document contains information on products under development. Austria Mikro Systeme International AG reserves the right to
change or discontinue this product without notice.
1
Functional Description
The Figure 1 shows the block diagram of the ASCell3912. The analog part of the ASCell3912
consists of a direct conversion receiver, a triple band RF synthesizer and the DC-cancellation.
The digital part includes the burst interference resistant protocol decoder the control logic and
the μC interface.
Figure 1:
Digital
Power
Supply
XO-SEL
I
Q
LC
+
LC
-
G
M
C
TE
ST
2
D_
CL
K
D_
E
N
DA
TA
VDD
GND
AGND
RF-
AVDD
XTAL+
RF+
XTAL-
DC-Offset
Bandwith
90°
DATA-
RECOVERY
10dB
OSC
PLL
XO
-Det
DEM
CTRL
AFC
SYNC
FIR
CLK
GEN
SETUP-
REGISTER
INTERFACE
RF-Power
%
n
RF
Power
Supply
PROTOCOL
DECODER
Scan
Test
XOT[3:0]
XO-CLK
RF-SEL
STATE REGISTER
Functional
Test
1/STR
μC
_C
LK
RE
_I
NT
W
AK
E_
UP
LNA
RFGND
TEST1
Sleeptime
control
Block diagram of the ASCell3912.
A
ASCell3912
相關PDF資料
PDF描述
ASD07H-12D12 Isolated and Regulated 7 WATT Open Frame DC/DC Converter
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