參數(shù)資料
型號(hào)： ASCELL3912
廠商： AUSTRIAMICROSYSTEMS AG
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： ER 10C 10#16 SKT RECP LINE
中文描述： SPECIALTY TELECOM CIRCUIT, PDSO20
封裝： TSSOP-20
文件頁(yè)數(shù)： 11/14頁(yè)
文件大?。?/td> 122K
代理商： ASCELL3912
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell – Preliminary Data Sheet
ASCell3912
Rev. A, February 2000
Page 11 of 14
Austria Mikro Systeme International AG
2.5
T
AMB
= 23 °C, VDD = 3.6 V, unless specified otherwise. GND is the 0 V reference.
Digital Pin Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
μC_CLK (μC clock output)
VOH
High level output voltage
IOH =-1 mA
VDD-0.5
-
V
VOL
Low level output voltage
IOL =1 mA
-
0.3
V
tr
Rise time
CLoad = 10 pF
20
ns
td
Fall time
CLoad = 10 pF
20
ns
jcc
Cycle to cycle jitter
+/-5
%
DATA(serial data input), D_EN (serial data enable input), D_CLK (serial data clock input)
VIH
High level input voltage
VDD-0.5
-
V
VIL
Low level input voltage
-
0.3
V
IIH
High level input current
VIH= VDD
1
μA
IIL
Low level input current
VIL =0 V
-1
μA
F
D_CLK
RE_INT (interrupt output); WAKEUP (μC wakeup output)
D_CLK frequency
3
kHz
VOH
High level output voltage
IOH = -1mA
VDD-0.5
-
V
VOL
Low level output voltage
IOL = 1mA
-
0.3
V
3
Pin-out Information
Note: pin numbers have arbitrary ordering and numbering - will be defined during design
Pin
Name
Type
Description
1
RF+
I
LNA input
2
RF-
I
LNA input
3
LC+
I/O
LNA tank
4
LC-
I/O
LNA tank
5
XTAL+
I
XTAL oscillator input
6
XTAL-
O
XTAL oscillator output
7
AVDD
P
Analog positive supply
8
AGND
P
Analog negative supply
9
GMC
I/O
Base-Band Low Pass frequency set
10
RFGND
I
RF GND
11
DGND
P
Digital negative supply
12
TEST1
I/O
pin for test purposes
13
TEST2
I/O
pin for test purposes
14
uC_CLK
O
Clock output for micro controller
15
RE_INT
O
Interrupt at first received data block and receive end
16
WAKEUP
O
Micro controller wake up; high during ongoing reception
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