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參數(shù)資料
| 型號： | ASCELL3912 |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | ER 10C 10#16 SKT RECP LINE |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO20 |
| 封裝： | TSSOP-20 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大小： | 122K |
| 代理商： | ASCELL3912 |
ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell – Preliminary Data Sheet
ASCell3912
Rev. A, February 2000
Page 6 of 14
Austria Mikro Systeme International AG
Figure 2:
μC-readout
WAKE_UP
Receiver-sleep-time =
(STR +1) * 20 ms
SYNC
13.80ms
DATA
12.28ms
SYNC
13.80ms
DATA
12.28ms
SYNC
13.80ms
DATA
12.28ms
SYNC
13.80ms
DATA
12.28ms
Receiver Wake up sequence
max. 22.25ms
XO-
Set
T
DET1
=26.08ms
T
X
=
Wake-Up
trigger
Wake up
RX
start
detection
TX-Start
Wake-Up
trigger
TX- stop
RX-sleep
T
INT
= 0.5ms
Data reception and store data
XO-
Set
SYNC
13.80m
DATA
Data reception
RX-
Status
TX-
Status
data detection
completed
shown for T
DET1
T
STOP
≤
30ms
RE_INT
T
BWI
≤
0.5ms
RX
DR
Interface-lines: Shown for T
DET1
Internal flags:
Shown for T
DET1
T
DET0
=12.28ms
T
DET2
=64.44ms
ì
Detection with 0 GSM-interferer
T
DET0
=12.28ms
ì
Detection with 1 GSM interferer or in 50% Duty Cycle ModeT
DET1
=26.08ms
ì
Detection with 2 GSM interferer
T
DET2
=64.44ms
ì
Active time after last useful data
T
STOP
≤
30ms
ì
Cristal Oscillator setup-time
T
XOS
=5ms
μC_CLK
T
CAI
= 16/F
CLK
ASCell3912 basic timing.
Note: The Interface timing and the timing of the internal flags are shown in Figure 2 for a detection time of T
DET1
.
1.2.3 Receiver Configuration
The configuration register can be loaded from a μC via the serial interface. The Table 2 below
shows the contents of the configuration register. Bit b0 is the first transmitted bit. The setup
contains the LNA set, frequency band and the sleep time interval of the receiver.
bit #
Name
Description
Configuration
Comments
0
LNA
LNA gain switch
L= LNA Gain is high
H= LNA Gain is -10dB
default
1..2]
FB[1:0]
Frequency band select with
FB1 is MSB
L, L (FB1, FB0) = 868.3 MHz
L, H = 433.92 MHz
H, L = 315 MHz
H, H = not used
default
3..8]
STR[5:0]
Sleep time interval set of
the receiver, with STR5 is
MSB
sleep
= (STR + 1) * 20ms
Note: for STR = 00h the
witing period between
two consecutive wake-
up cycles will be 148 bit.
Table 2: Format of the configuration Register
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