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參數(shù)資料
| 型號： | AS8201 |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | TTP/C-C1 Communications Controller |
| 中文描述： | 2 CHANNEL(S), 2M bps, SERIAL COMM CONTROLLER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 247K |
| 代理商： | AS8201 |
TTP/C-C1 Communications Controller Data Sheet
AS8201
Rev. NC, October 1999
Page 9 of 13
Austria Mikro Systeme International AG
microtick
t
ct
ram_web
ram_ceb
t
ce
ram_address
XXX
t
a
ram_data
XXXX
t
rwct
address stable
data stable
Figure 4: Write Cycle Timing
Addresses, data and RAM_WEB have to be stable before the falling edge of RAM_CEB.
RAM_CEB has to be applied for 2 microticks. Addresses, data, and RAM_WEB have to be
applied for 3 microticks.
Parameter
controller cycle time
duration of chip enable
address time
data valid time
read write cycle time
Symbol
t
ct
t
ce
t
a
t
dv
t
rwct
Min
Typ
50ns
100ns
150ns
300ns
300ns
Max
87.5ns
137.5ns
112.5ns
162.5ns
Table 3: Host Interface Timing
Reset and Oscillator
Pin Name
XIN0
XENA0
XOUT0
XIN1
XOUT1
XENA1
RESETB
MICROTICK
mode
in
in
out
in
out
in
in
out
width
1
1
1
1
1
1
1
1
Comment
controller oscillator input
controller clock enable
controller oscillator output
bus guardian oscillator input
bus guardian oscillator output
bus guardian clock enable
external reset
controller clock (inverted)
Table 4: Reset and Oscillator Ports
External Reset Signal
To issue a reset of the chip the RESETB port has to be driven low for at least
200
μ
s. After
power-up the reset must overlap the build-up time of the oscillator circuit.
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