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參數(shù)資料
| 型號： | AS8201 |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | TTP/C-C1 Communications Controller |
| 中文描述： | 2 CHANNEL(S), 2M bps, SERIAL COMM CONTROLLER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大小： | 247K |
| 代理商： | AS8201 |
TTP/C-C1 Communications Controller Data Sheet
AS8201
Rev. NC, October 1999
Page 8 of 13
Austria Mikro Systeme International AG
lines signal to host CPU the global synchronous time of the TTP network and determine when
to deliver, resp. to fetch data from the host interface. One of the lines may be connected to a
interrupt inputs of the host CPU.
Pin Name
RAM_ADDRESS
RAM_DATA
RAM_CEB
RAM_WEB
RAM_OEB
RAM_READYB
TIME_OVERFLOW
TIME_SIGNAL
TIME_TICK
mode
in
inout (tri)
in
in
in
out
out
out
out
width
11
16
1
1
1
1
1
1
1
comment
DPRAM address bus, 11 bit
DPRAM data bus, 16 bit
DPRAM chip enable
DPRAM write enable
DPRAM output enable
DPRAM ready
overflow of global time
CNI time signal
macrotick
Table 2 Host Interface Ports
microtick
t
ct
ram_data
XXX
t
dv
ram_address
XXX
t
a
ram_ceb
t
ce
t
rwct
address stable
ram_web
Figure 3: Read Cycle Timing
Addresses and RAM_WEB have to be stable before the falling edge of RAM_CEB. RAM_CEB
has to be applied for 2 microticks. Addresses and RAM_WEB have to be applied for 3
microticks. Data can be read from RAM_DATA after 6 microticks. RAM_OEB drives the result
of the (last) read operation to the RAM_DATA bus.
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