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參數(shù)資料
| 型號： | AS8201 |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | TTP/C-C1 Communications Controller |
| 中文描述： | 2 CHANNEL(S), 2M bps, SERIAL COMM CONTROLLER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 247K |
| 代理商： | AS8201 |
TTP/C-C1 Communications Controller Data Sheet
AS8201
Rev. NC, October 1999
Page 6 of 13
Austria Mikro Systeme International AG
Recommended Operating Conditions
PARAMETER
DC Supply Voltage
Circuit Ground
Static Supply Current
Operating Supply
Current
Main clock frequency
Bus Guardian clock
frequency
Ambient Temperature
SYMBOL MIN
VDD
VSS
IDDS
IDD
TYP
5.0 V
0.0 V
40
μ
A
110 mA
MAX
5.5 V
0.0 V
100
μ
A
160 mA
NOTE
1)
4.5 V
0.0 V
----
----
2)
fCLK = 20 MHz, VDD = 5.5 V
3)
CLK
CLK2
5 MHz
4 MHz
20 MHz
16 MHz
oscillator pins XIN0, XOUT0
oscillatpr pins XIN1, XOUT1
Ta
-40 oC
+125 oC
1)
1) The input and output parameter values in this table are directly related to ambient temperature and DC supply
voltage. A temperature range other Ta
min
to Ta
max
or a supply voltage range other than VDD
min
to VDD
max
will
affect these values and must be evaluated extra.
2) Static supply current IDDS is exclusive of input/output drive requirements and is measured at maximum VDD
with the clocks stopped and all inputs tied to VDD or VSS, configured to draw minimum current.
3) Operating current is exclusive of input/output drive requirements and is measured at maximum VDD and maxi-
mum clock frequency 20 MHz.
DC Characteristics and Voltage Levels
CMOS I/O levels for specified voltage and temperature range unless otherwise noted.
Inputs Pins
Pin Name
Vil
max
30%
VDD
Vih
min
70%
VDD
Iil (1)
min
NA
Iih(2)
min
NA
NOTE
max
-1.0
μ
A
max
1.0
μ
A
All inputs and IO pins
(except: ROM_READY,
RXD[0], RXD[1], FTEST,
FTEST_IEN, TEST_SE)
ROM_READY, RXD[0],
RXD[1]
FTEST, FTEST_IEN,
TEST_SE
Notes:
1) Iil ist tested at VDDmax and Vin = 0
2) Iih ist tested at VDDmax and Vin = VDDmax
3) CMOS input levels are in percentage of VDD
4)
Output Pins
CMOS input (3)
30%
VDD
30%
VDD
70%
VDD
70%
VDD
-50
μ
A
NA
-160
μ
A
NA
NA
NA
CMOS with pull
up (3)
CMOS with pull
down (3)
30
μ
A
160
μ
A
Pin Name
Vol
V
0.4
Voh
V
4.0
Iol (1)
mA
4.0
Ioh(2)
mA
-4.0
Ioz(3)
μ
A
NA
NOTE
All output pins
(except XOUT0,XOUT1)
All I/O pins
1) Vol, Iol is tested at VDD = 4.5V
2) Voh, Ioh is tested at VDD = 4.5V
3) Ioz is tested at VDD = 5.5V
CMOS output
0.4
4.0
4.0
-4.0
+/-10
CMOS output, Tristate
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