參數(shù)資料
型號(hào): AS8201
廠商: AUSTRIAMICROSYSTEMS AG
元件分類: 微控制器/微處理器
英文描述: TTP/C-C1 Communications Controller
中文描述: 2 CHANNEL(S), 2M bps, SERIAL COMM CONTROLLER, PQFP120
封裝: PLASTIC, QFP-120
文件頁數(shù): 2/13頁
文件大小: 247K
代理商: AS8201
TTP/C-C1 Communications Controller Data Sheet
AS8201
Rev. NC, October 1999
Page 2 of 13
Austria Mikro Systeme International AG
Key Features
First dedicated controller supporting TTP/C (time triggered protocol class C)
Device for building up TTP/C nodes in a TTP/C local area networks (clusters).
Suited for dependable distributed real-time systems with guaranteed response time
application examples:
automotive: braking, steering, vehicle dynamics control, drive train control
industry: air plane flap control, rail way points
Bit data rate 2 Mbits/s @ clock 20 MHz, 5.0V
Fabricated in 0.6u CMOS process, automotive temperature range of -40 to 125deg C
1k x 16 RAM message, status and control area
RAM for instruction code and configuration data
16 bit non-multiplexed host CPU interface
16 bit RISC architecture
external firmware (FLASH memory) conforming the TTP/C specification
automatic booting after power on
software tools, design-in support, development boards available (
http://www.tttech.com)
120 pin PQFP Package
Description
The TTP/C-C1 communications controller is the first integrated device supporting serial
communication according to the TTP/C specification (time triggered protocol class C). It
performs all communications tasks such as reception and transmission of messages in a
TTP/C cluster without interaction of the host CPU.
TTP/C provides mechanisms that allow the deployment in high-dependability distributed real-
time systems. It provides the following services:
predictable transmission of messages with minimal jitter
fault-tolerant distributed clock synchronisation
consistent membership service with small delay
masking of single faults
RXD[1:0]
BDE[1:0]
XENA1
XIN1
XOUT1
TXD[1:0]
CTS[1:0]
OE[1:0]
TEST_SE
FTEST
FTEST_IEN
LED[7:0]
Boot ROM
Interface
RAM_DATA[15:0]
RAM_ADDRESS[10:0]
RAM_CEB
RAM_OEB
RAM_WEB
RAM_READYB
TIME_OVERFLOW
TIME_SIGNAL
TIME_TICK
MICROTICK
XENA0
XIN0
XOUT0
RESETB
ROM_ADDRESS[16:0]
ROM_DATA[15:0]
ROM_RESETB
ROM_CEB
ROM_OEB
ROM_WEB
ROM_READY
Quarz or
Oscillator
Controller
network
interface
(CNI)
TTP/C-C1
protocol
processor core
Instruction
memory
Network
configuration
memory
(MEDL)
TTP/C
bus -
Meadia
Drivers
Bus
guardian
Receiver
Transmitter
Reset &
Time
base
Host
processor
Interface
Test
Inter-
face
Figure 1 Block Diagramm
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