參數(shù)資料
型號(hào): AS6C1008-55PCN
廠商: ALLIANCE MEMORY INC
元件分類: SRAM
英文描述: IC,AS6C1008-55PCN,DIP-32 LP SRAM,55NS,128K X 8,2.7-5.5V
中文描述: 128K X 8 STANDARD SRAM, 55 ns, PDIP32
封裝: 0.600 INCH, ROHS COMPLIANT, PLASTIC, DIP-32
文件頁數(shù): 9/14頁
文件大?。?/td> 2717K
代理商: AS6C1008-55PCN
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA = 25C
CAPACITANCE (TA= 25 , f
= 1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX
UNIT
C
e
c
n
a
ti
c
a
p
a
C
t
u
p
n
I
IN
-
6
pF
Input/Output Capacitance
CI/O
-
8
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
V
o
t
V
2
.
0
s
l
e
v
e
L
e
s
l
u
P
t
u
p
n
I
CC
- 0.2V
s
n
3
s
e
m
i
T
ll
a
F
d
n
a
e
s
i
R
t
u
p
n
I
Input and Output Timing Reference Levels
1.5V
C
d
a
o
L
t
u
p
t
u
O
L
=30pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
AS6C1008-55
PARAMETER
SYM.
MIN.
MAX.
UNIT
Read Cycle Time
tRC
55
-
ns
Address Access Time
tAA
-
55
ns
Chip Enable Access Time
tACE
-
55
ns
Output Enable Access Time
tOE
-
30
ns
Chip Enable to Output in Low-Z
tCLZ*
10
-
ns
Output Enable to Output in Low-Z
tOLZ*
5
-
ns
Chip Disable to Output in High-Z
tCHZ*
-
20
ns
Output Disable to Output in High-Z
tOHZ*
-
20
ns
Output Hold from Address Change
tOH
10
-
ns
(2) WRITE CYCLE
PARAMETER
SYM.
MIN.
MAX.
UNIT
Write Cycle Time
tWC
55
-
ns
Address Valid to End of Write
tAW
50
-
ns
Chip Enable to End of Write
tCW
50
-
ns
Address Set-up Time
tAS
0
-
ns
Write Pulse Width
tWP
45
-
ns
Write Recovery Time
tWR
0
-
ns
Data to Write Time Overlap
tDW
25
-
ns
Data Hold from End of Write Time
tDH
0
-
ns
Output Active from End of Write
tOW*
5
-
ns
Write to Output in High-Z
tWHZ*
-
20
ns
*These parameters are guaranteed by device characterization, but not production tested.
AS6C1008-55
February 2007
128K X 8 BIT LOW POWER CMOS SRAM
AS6C1008
02/February/07, v 1.0
Alliance Memory Inc.
Page 4 of 14
相關(guān)PDF資料
PDF描述
AS6C4008-55PCN IC,AS6C4008-55PCN,DIP-32 LP SRAM,55NS,512K X 8,2.7-5.5V
AS6C4008-55SIN IC,AS6C4008-55SIN,SOP-32 LP SRAM,55NS,512K X 8,2.7-5.5V
AS6C4008-55STIN IC,AS6C4008-55STIN,STSOP-32 LP SRAM,55NS,512K X 8,2.7-5.5V
AS6C4008-55TIN IC,AS6C4008-55TIN,TSOP-32 LP SRAM,55NS,512K X 8,2.7-5.5V
AS6C6264-55PCN IC,AS6C6264-55PCN,DIP-28 LP SRAM,55NS,8K X 8,2.7-5.5V
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AS6C1008-55SINLTR 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mb, 2.7V-5.5V, 55ns 128K x 8 Asynch 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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