參數(shù)資料
型號： AS5130-ASST-500
廠商： ams
文件頁數(shù)： 9/33頁
文件大?。?/td> 4323K
描述： IC ENCODER ROTORY 8-BIT 16-SSOP
標(biāo)準(zhǔn)包裝： 500
傳感范圍： 32mT ~ 75mT
類型： 線性，旋轉(zhuǎn)編碼器 - 可編程
電源電壓： 4.5 V ~ 5.5 V
電流 - 電源： 24mA
輸出類型： 模擬，比率
特點： 可編程
工作溫度： -40°C ~ 125°C
封裝/外殼： *
供應(yīng)商設(shè)備封裝： *
包裝： *
www.austriamicrosystems.com/AS5130
Revision 1.12
8 - 41
AS5130
Datasheet - Electrical Characteristics
6.1 Timing Characteristics
TAMB
 
= -40篊 to 125篊, unless otherwise noted.
6.2 Magnetic Input Range
The magnetic input range is defined by the AGC loop. This regulating loop keeps the Hall sensor output in the optimum range for low SNR by
adjusting the Hall bias current. This loop can adjust to a magnetic field strength variation of ?8%. The AGC output voltage is an indicator for the
magnetic field.
The nominal magnetic field for a balanced AGC is defined by the Hall bias and the Hall sensitivity and can be set by a variable gain in the signal
path. The gain can be set in 8 steps in the OTP or by the SSI in a mirror register. The resulting magnetic input range is a value of B
nominal
?8%
inside of a range of 32mT &75mT, if the trimming is performed by the customer.
Table 4. Timing Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t0
Rising CLK to CS
15
--
ns
t1
Chip select to positive edge of CLK
15
--
ns
t2
Chip select to drive bus externally
--
--
ns
t3
Setup time command bit,
Data valid to positive edge of CLK
30
ns
t4
Hold time command bit,
Data valid after positive edge of CLK
30
ns
t5
Float time,
Positive edge of CLK for last command bit to
bus float
30
CLK/2
ns
t6
Bus driving time,
Positive edge of CLK for last command bit to
bus drive
CLK/2
+0
CLK/2
+30
ns
t7
Setup time data bit,
Data valid to positive edge of CLK
CLK/2
+0
CLK/2
+30
ns
t8
Hold time data bit,
Data valid after positive edge of CLK
CLK/2
+0
CLK/2
+30
ns
t9
Hold time chip select,
Positive edge CLK to negative edge of chip
select
30
ns
t10
Bus floating time,
Negative edge of chip select to float bus
0
30
ns
t
TO
Timeout period in 2-wire mode (from rising
edge of CLK)
20
24
祍
Table 5. Magnetic Input Range
Setting
0
1
2
3
4
5
6
7
Binary
000
001
010
011
100
101
110
111
Gain A
0.9
1.05
1.2
1.4
1.65
1.9
2.2
2.55
B
limit
Max. 75mT
Min. 32mT
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