參數(shù)資料
型號(hào): AS5130-ASST-500
廠商: ams
文件頁數(shù): 24/33頁
文件大?。?/td> 4323K
描述: IC ENCODER ROTORY 8-BIT 16-SSOP
標(biāo)準(zhǔn)包裝: 500
傳感范圍: 32mT ~ 75mT
類型: 線性,旋轉(zhuǎn)編碼器 - 可編程
電源電壓: 4.5 V ~ 5.5 V
電流 - 電源: 24mA
輸出類型: 模擬,比率
特點(diǎn): 可編程
工作溫度: -40°C ~ 125°C
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
www.austriamicrosystems.com/AS5130
Revision 1.12
23 - 41
AS5130
Datasheet - Detailed Description
If the AS5130 is cycled between active and reduced current mode, a substantial reduction of the average supply current can be achieved. The
minimum dwelling time in active mode is the wake-up time. The actual active time depends on how much the magnet has moved while the
AS5130 was in reduced power mode. The angle data is valid, when the status bit LOCK has been set (see Table 9). Once a valid angle has been
measured, the AS5130 can be put back to reduced power mode. The average power consumption can be calculated as:
I
avg
 =
  sampling interval = t
on
 + t
off
(EQ 7)
Where:
I
avg
 = Average current consumption
I
active
 = Current consumption in active mode
I
power_down
 = Current consumption in reduced power mode
t
on
 = Time period during which the chip is operated in active mode
t
off
 = Time period during which the chip is in reduced power mode
Reducing Power Supply Peak Currents. An optional RC-filter (Rx/Cx) may be added to avoid peak currents in the power supply line when 
the AS5130 is toggled between active and reduced power mode. Rx must be chosen such that it can maintain a VDD voltage of 4.5  5.5V under
all conditions, especially during long active periods when the charge on Cx has expired. Cx should be chosen such that it can support peak
currents during the active operation period. For long active periods, Cx should be large and Rx should be small.
7.8.2   Power Cycling Mode
The power cycling method shown in Figure 17 cycles the AS5130 by switching it on and off, using an external PNP transistor high side switch.
The current consumption in off-mode is zero. It also has the longest start-up time of all modes, as the chip must always perform a cold start
from zero, which takes about 2ms (Compare with Low Power Mode on page 22).
Figure 17. Power Cycling Mode
The optional filter Rx/Cx may again be added to reduce peak currents in the 5V power supply line (see Reducing Power Supply Peak Currents 
on page 23).
active

t
on
I
powerdown

t
off
+
t
on
t
off
+
-------------- ----------------- ----------------- ----------------- - -
VDD
VSS
micro
controller
AS5130
100n
VSS
+5V
VDD
CS
VDD
DCLK
DIO
VSS
AS5130
C1
S
N
I
on
0
t
on
t
off
on/off
Rx
10k
t
on t
off
Cx
>礔
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