參數(shù)資料
型號: AS5130-ASST-500
廠商: ams
文件頁數(shù): 7/33頁
文件大?。?/td> 4323K
描述: IC ENCODER ROTORY 8-BIT 16-SSOP
標(biāo)準(zhǔn)包裝: 500
傳感范圍: 32mT ~ 75mT
類型: 線性,旋轉(zhuǎn)編碼器 - 可編程
電源電壓: 4.5 V ~ 5.5 V
電流 - 電源: 24mA
輸出類型: 模擬,比率
特點(diǎn): 可編程
工作溫度: -40°C ~ 125°C
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
www.austriamicrosystems.com/AS5130
Revision 1.12
6 - 41
AS5130
Datasheet - Electrical Characteristics
6 Electrical Characteristics
TAMB
 
= -40篊 to +125篊, unless otherwise noted.
Table 3. Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VDD
Positive Supply Voltage
Except OTP programming
4.5
5
5.5
V
DVDD
Polling Mode Supply Voltage
3.6
5
5.5
V
IDD
Power Supply Current
14
24
mA
I
off
Power Down Mode
1.4
2
mA
N
Resolution
8
bit
1.406
deg
T
PwrUp
Power Up Time
Startup from zero
2000
Startup with preset AGC - Polling mode
(Supplied during t
off
 phase of VDD from the
external buffer capacitor via DVDD pin)
250
Startup from low power mode
150
t
da
Propagation Delay
Analog signal path; over full temperature
range
15
17
t
dd
Tracking rate
Step rate of tracking ADC;
1 step = 1.406?/DIV>
0.85
1.15
1.45
t
delay
Signal Processing Delay
Total signal processing delay, Analog +
Digital + SSI readout
(t
da
 + t
dd
 + t
SSI
)
21.55
T
Analog filter time constant
Internal lowpass filter
4.1
6.6
12.5
INL
cm
Accuracy
Centered Magnet
-2
2
Within horizontal displacement radius (see
parameters for magnet)
-3
3
TN
Transition Noise
rms (1 sigma)
0.235
POR
r
Power-On-Reset levels
VDD rising
3.7
4
4,3
V
POR
f
VDD falling
3.4
3.7
3.9
V
Parameters for Magnet
n
Rotational Speed
Frequencies above 1000 rpm causes an
additional not specified DNL Error
-30000
30000
rpm
MD
Magnet diameter
Diametrically magnetized
6
mm
MT
Magnet thickness
2.5
mm
B
i
Magnetic input range
Valid for use of full range of sensitivity
32
75
mT
s
Magnetic Sensitivity of AGC
AGC value available at SSI
0.5
5
LSB/mT
B
DC
Magnetic Offset
Magnetic stray field without gradient
4
mT
DC/AC Characteristics for Digital Inputs and Outputs
CMOS Input
V
IH
High level Input voltage
0.7 x
VDD
V
V
IL
Low level Input Voltage
0.3 x
VDD
V
I
LEAK
Input Leakage Current
1
礎(chǔ)
CMOS Output
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