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參數(shù)資料
| 型號： | AS4LC8M8S0-75TC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
| 中文描述： | 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大小： | 566K |
| 代理商： | AS4LC8M8S0-75TC |
4
ALLIANCE SEMICONDUCTOR
7/5/00
AS4LC4M16S0
AS4LC16M4S0
Commands
1
OP = operation code.
A0~A11 and BA0~BA1 program keys.
MRS can be issued only when all banks are precharged. A new command can be issued 1 clock cycle after MRS.
Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic.
Auto/self refresh can only be issued after all banks are precharged.
BA0~BA1: bank select addresses.
If A10/AP is High at row precharge, BA0 and BA1 are ignored and all banks are selected.
During read, write, row active, and prechage:
If BA0 and BA1 are Low, Bank A is selected.
If BA0 = Low and BA1 = High, Bank B is selected.
If BA0 = High and BA1 = Low, Bank C is selected.
If BA0 and BA1 are High, Bank D is selected.
A new read/write command to the same bank cannot be issued during a burst read/write with auto precharge.
A new row active command can be issued after t(t
RP
/t
CK
+ BL +) cycles.
Burst stop command valid at every burst length.
DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0).
Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2).
2
3
4
5
6
7
Command
Register
CKE
n-1
CKE
n
H
*
H
H
CS
L
L
L
L
H
L
RAS
L
L
L
H
X
L
CAS
L
L
L
H
X
H
WE
L
H
H
H
X
H
DQM
X
X
X
X
X
X
BA0/
BA1
A10
Op code
A9–A0
DQ
X
Note
1,2
3
3
3
3
Mode register set
Auto refresh
* V: Valid; X: Dont care; H: Logic high; L: Logic low.
H
H
L
Refresh
–
–
–
–
V
X
–
–
–
–
X
Self
refresh
Entry
Exit
L
H
Bank activate
H
H
row address
L
column
address
H
L
column
address
H
X
L
H
X
Read
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
H
H
L
H
L
H
X
V
X
4
4,5
4
4,5
6
Write
H
H
L
H
L
L
X
V
Valid
Burst stop
H
H
L
H
H
L
X
Active
Precharge
Selected bank
All banks
H
H
L
L
H
L
X
V
X
X
X
4
Clock suspend or
active power down
Entry
H
L
H
L
X
H
L
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
X
X
X
X
Exit
L
H
Precharge power
down mode
Entry
H
L
X
X
X
X
X
Exit
L
H
DQM
Write enable/output
enable
Write inhibit/Output
High-Z
H
H
X
X
X
X
H
X
X
X
X
7
No operation command
H
X
H
L
X
H
X
H
X
H
X
X
X
X
X
X
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