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參數(shù)資料
| 型號： | AS4LC8M8S0-75TC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
| 中文描述： | 8M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 566K |
| 代理商： | AS4LC8M8S0-75TC |
16
ALLIANCE SEMICONDUCTOR
7/5/00
AS4LC4M16S0
AS4LC16M4S0
write interrupted by write (BL = 4)
t
CCD
= CAS to CAS delay (= 1 CLK)
t
CDL
= last address in to new column addres delay (= 1 CLK)
write interrupted by read (CL = 2, BL = 4)
t
CCD
= CAS to CAS delay (= 1 CLK)
t
CDL
= last address in to new column addres delay (= 1 CLK)
read interrupted by write (CL = 3, BL = 4)
*
To prevent bus contention, maintain a gap between data in and data out.
Burst termination
Burst operations may be terminated with a Read, Write, Burst Stop, or Precharge command. When Burst Stop is asserted
during the read cycle, burst read data is terminated and the data bus goes to High Z after CAS latency. When Burst Stop is
asserted during the write cycle, burst write data is terminated and the databus goes to High Z simultaneously.
Burst stop command waveform, read cycle
(BL = 8)
CLK
CMD
ADD
DQ
DA
0
DB
0
DB
1
DB
2
DB
3
A
0
B
0
Write data
Write data
t
CCD
t
CDL
t
CDL
CLK
CMD
ADD
DQ (CL2)
DQ (CL3)
Write data
Read data
A
B
DA
0
QB
0
QB
1
QB
2
QB
3
DA
0
QB
0
QB
1
QB
2
QB
3
t
CCD
CLK
CMD
DQM
DQ
Read data
Write data*
D
0
D
1
D
2
D
3
Q
0
CLK
CMD
DQ (CL = 2)
DQ (CL = 3)
Read data
Burst stop
Q
0
Q
1
Q
2
Q
0
Q
1
Q
2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4LC8M8S0-8TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
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| AS-4PD | 制造商:RALTRON 制造商全稱:RALTRON 功能描述:SURFACE MOUNT MICROPROCESSOR CRYSTAL |
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