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參數(shù)資料
| 型號： | AS4LC4M16S0 |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 3.3V 4M × 16 CMOS Synchronous DRAM(3.3V 4M × 16 CMOS同步動態(tài)RAM) |
| 中文描述： | 3.3分× 16的CMOS同步DRAM（3.3分× 16的CMOS同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 566K |
| 代理商： | AS4LC4M16S0 |
AS4LC8M8S0
AS4LC4M16S0
7/5/00
ALLIANCE SEMICONDUCTOR
9
AC parameters common to all waveforms (continued)
Notes
1
2
3
4
5
6
7
Minimum clock cycles = (Minimum time / clock cycle time) rounded up.
Minimum delay required to complete write.
Column address change allowed every cycle.
Parameters dependent on CAS latency.
If clock rising time
>
1ns, (tr/2-0.5)ns should be added to parameter.
If (tr and tf)
>
1ns, [(tr+tf)/2-1]ns should be added to parameter.
Outputs measured at 1.5V with 50pF load only without resistive termination.
Burst sequence
(BL = 4)
Burst sequence
(BL = 8)
Sym
t
DQD
t
DQM
DQM to data mast during writes
DQM to data high Z during
Parameter
CAS
latency
-75
-8
-10 F
-10
Unit
CLK
CLK
Notes
Min Max
1
0
Min
1
0
Max
–
–
Min
1
0
Max
–
–
Min
1
0
Max
–
–
DQM to input data delay
–
–
t
DQZ
reads
2
–
2
–
2
–
2
–
CLK
t
DWD
Write command to input data
delay
Data-in to active command
Load mode register to active/
refresh command
0
–
0
–
0
–
0
–
CLK
t
DAL
5
–
5
–
5
–
5
–
CLK
t
MRD
1
–
1
–
1
–
1
–
CLK
t
ROH
Data-out high Z from
precharge/burst stop command
3
2
3
2
–
–
3
2
–
–
3
2
–
–
3
2
–
–
CLK
CLK
4
4
t
CKED
CKE to CLOCK disable or power-
down entry mode
CKE to clock enable or power-
down exit mode
1
–
1
–
1
–
1
–
CLK
t
PED
1
–
1
–
1
–
1
–
CLK
Initial address
Sequential
1
2
3
0
Interleave
1
0
3
2
A1
0
0
1
1
A0
0
1
0
1
0
1
2
3
2
3
0
1
3
0
1
2
0
1
2
3
2
3
0
1
3
2
1
0
Initial address
A1
0
0
1
1
0
0
1
1
Sequential
3
4
5
6
7
0
1
2
Interleave
3
2
1
0
7
6
5
4
A2
0
0
0
0
1
1
1
1
A0
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS4LC4M16S0-75TC | 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
| AS4LC4M16S0-8TC | 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
| AS4LC8M8S0 | 3.3V 8M × 8 CMOS Synchronous DRAM(3.3V 8M × 8 CMOS同步動態(tài)RAM) |
| AS4LC4M16S0-10FTC | 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
| AS4LC4M16S0-10TC | 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4LC4M16S0-10FTC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
| AS4LC4M16S0-10TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
| AS4LC4M16S0-75TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
| AS4LC4M16S0-8TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM |
| AS4LC4M4 | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:4M x 4 CMOS DRAM WITH FAST PAGE MODE, 3.3V |
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