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參數(shù)資料
| 型號： | AS2702-20T |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | 其它接口 |
| 英文描述： | AS-Interface Slave IC |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 119K |
| 代理商： | AS2702-20T |
AS-Interface Slave IC
AS2702 (SAP4.1)
Rev. C, January 2001
Page 9 of 18
The dc-parameters of the data port pins D3
, …, D0 are specified as follows:
6\PERO
IOUTLO
3DUDPHWHU
Sink current @ output L
PLQ
10
PD[
8QLW
mA
1RWH
VOUT =
1V
1
2
IOUTHI
VSCHLT
VIN
Leakage current @ output off
Input threshold voltage
Acceptable input voltage @
output off
- 1
2.5
- 0.3
1
μA
V
V
3.5
40
Notes:
1
Output stage is low-side open-drain; ext. pull-up resistor required as no pull-up
structure on chip
No hysteresis implemented
2
To govern the data transfer at data port D3, …,D0 strobe pin DSTBn is equipped with a low-
side open-drain output switch plus a passive high-side current source with a nom. 10 μA pull-
up current capability.
However a second function is assigned to the DSTBn pin which requires it to be input as well:
if a low-pulse is imposed on DSTBn by external means with a pulse width of at least 50 to 100
ms, the slave device will be put in RESET condition, as described in section “Reset”.
The dc-and timing parameters of strobe pin DSTBn are specified as follows:
6\PERO
IOUTLO
IOUTHI
IINLO
VSCHLT
VIN
3DUDPHWHU
Sink current @ output L
Leakge current @ output off
Input current @ VIN = 1V
Input threshold voltage
Acceptable input voltage @
output off
DSTBn L-phase width, not
triggering RESET
DSTBn L-phase width, trig-
gering RESET
Stray capacitance
PLQ
10
- 10
- 5
1.5
- 0.3
PD[
8QLW
mA
μA
μA
1RWH
VOUT = 1V
VOUT = 5V
1
2
10
- 20
3.5
40
V
V
tNORESET
50
ms
tRESET
100
ms
CPINEXT
20
pF
Notes:
1
DSTBn is equipped with an on-chip pull-up current source, which ensures
a sufficiently fast LH-edge upon output switch-off in open-pin condition,
to prevent erroneous RESET triggering.
If DSTBn has an external load connected to it,
an additional external pull-up resistor may be needed
to prevent erroneous RESET triggering upon output switch-off
No hysteresis implemented
2
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