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| 型號： | AS2702-20T |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | 其它接口 |
| 英文描述： | AS-Interface Slave IC |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 119K |
| 代理商： | AS2702-20T |
AS-Interface Slave IC
AS2702 (SAP4.1)
Rev. C, January 2001
Page 10 of 18
L3DUDPHWHUSRUWSLQV33DQGSDUDPHWHUVWUREHSLQ367%Q
(Note that parameter port pins P3
, …, P0 are only available on AS2702 package option SOIC
20, not on the SOIC 16 option.)
The transfer of data at P3, …, P0 and the supporting strobe action at pin PSTBn takes place
similarly as at D3, …, D0 resp. DSTBn.
Each parameter port pin P3, …, P0 is equipped with both a low-side open-drain output switch
plus a passive, but switchable high-side current source with a nom. 10 μA pull-up current ca-
pability, and with an input stage.
Though equipped for bidirectional data transfer as D3, …, D0, the parameter port is less flexi-
ble than the data port.
Basically the parameter port is set to behave portwise as
output, or
input
depending on the IO-configuration code, written into and stored in the slave device.
The timing of the data transfer is presented in fig. 3.
Strobe signal PSTBn flags and governs the data transfer as follows:
ia) parameter port is set ‘output’:
output data become valid upon the HL-edge of the strobe and will remain so until the
next HL-edge, hence during the entire strobe cycle;
ib) parameter port is set ‘input’:
input data to be valid within a specific time window relative to the HL-edge of the
strobe, after completion of the strobe’s L-phase.
Output data as per ia) could be easily latched with the LH-edge of strobe PSTBn, if at all nec-
essary.
Fig. 3: Timing of data transfer at parameter port P3, …, P0 relative to strobe PSTBn
Parameter out Parameter out
Data in
t
STB
t
PSTBn
t
INPmin
t
INPmax
Px
Px
PSTBn
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