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| 型號： | AN2933 |
| 英文描述： | Understanding the eTPU Channel Hardware |
| 中文描述： | 理解硬件頻道的eTPU |
| 文件頁數(shù)： | 37/40頁 |
| 文件大小： | 741K |
| 代理商： | AN2933 |
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Channel Service Request
Understanding the eTPU Channel Hardware, Rev. 0
Freescale Semiconductor
37
An uncleared channel latch may continually request service. This may not block any other channel from
being serviced, but it will consume all the idle cycles of the eTPU. Depending on the priority of the
channel, this will have some effect on the latency of all other channels requesting service.
5.3
Timing the Channel Latch Clearing
In many situations, the channel service routine will calculate a match at a time which is in the past. This
would be an artifact of the algorithm driving the channel and might be perfectly acceptable for the system.
However, in this case, care must be taken in the timing of the match service routine to ensure that the MRL
is cleared at the proper time.
The eTPU enables a match by setting the MRLE when the ERT is written to the match register. The MRL
is cleared by a specific command. If the match is enabled too early, a past due match will be satisfied, and
the MRLE will be cleared. Then when the corresponding MRL is cleared, the new match will be lost.
On the other hand, if the MRL is cleared too early, it is possible that it will be set again before the match
register was written. This is an unlikely situation, since if the MRL was set, the MRLE should be cleared.
However, improper coding in a handling routine can give rise to the situation.
If matches were enabled, and a match occurs simultaneously with the rewriting of the match register, the
“old” match will be recognized, MRL will be set again, and the MRLE will also be set, enabling a
subsequent new match on the new value.
If the MRL is cleared in the same instruction as the new match value is written, the MRL cannot be
subsequently set except by matching the new register value. This is the preferred coding, and it can be
effected by grouping the
WriteErtAToMatchAAndEnable()
with the
ClearMatchALatch()
instructions in
the source code.
Matches can be disabled by the microcode in two different ways--note the differences. In the entry vector
of each thread is a one-bit field which allows the user to disable all matches during the duration of the
thread. This option in the entry vector is evoked by including
DisableMatchesInThread()
or alternately
match_disable()
at the beginning of the thread microcode sequence. This operation blocks the signal from
the MRL, so any temporary match conditions that are cleared before the end of the thread will not set the
MRL.
The thread can also assert
DisableMatchDetection()
during the thread. This clears both the MRLEs, and
the operation is not negated simply by ending the thread. Each MRLE that is cleared must be subsequently
re-enabled by
WriteErtAToMatchAAndEnable()
or
WriteErtBToMatchBAndEnable()
. One caution should
be raised here. The setting of the MRLE also writes the ERT to the match register. The desired match value
may have to be read and saved before other operations are performed.
The TDL is set only by the transition to the selected level or by sampling the pin at a match compare, not
by the level itself. A transition set on the rising edge and subsequently cleared will not be set again until
the pin falls and rises again. If the instruction negating TDL occurs simultaneously with the transition, the
TDL will be negated, but the dependent captures and/or pin actions will occur.
Finally, there is no microinstruction that tests and clears the MRLs or TDLs simultaneously, so there can
be no ambiguity introduced by compiler instruction packing.
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