參數(shù)資料
型號： AN2933
英文描述： Understanding the eTPU Channel Hardware
中文描述： 理解硬件頻道的eTPU
文件頁數(shù)： 2/40頁
文件大小： 741K
代理商： AN2933
Understanding the eTPU Channel Hardware, Rev. 0
Architecture of the eTPU Channel
Freescale Semiconductor
2
approach, and most TPU applications can be easily ported to the eTPU.
The TPU was programmed in microcode, and the complexity of the language made the device difficult to
learn and tedious to program. The enhancements in the eTPU have made the newer device considerably
more complex to use than the TPU. To offset the increased complexity, Freescale has teamed with tools
vendors to provide a set of eTPU development tools to enable the engineer to program the device in C.
This has proved to increase code productivity 2-3 times, while ensuring that future devices can be source
code compatible with eTPU.
The three major steps in the development of an eTPU system are the following:
1. Interfacing the channel control logic to the application
2. Writing the eTPU procedural code to control the channel logic
3. Interfacing the eTPU code to the host application
This note addresses the first step of that process. In fact, understanding the channel logic is the key to
applying the eTPU in a wide range of systems.
2
Architecture of the eTPU Channel
Like the TPU, the eTPU is organized as a single processing engine tightly coupled to a number of channels
each with independent logic interfaced to input and output pins. In the TPU channel, each input/output pin
was connected to an output compare and an input capture register. The enhancements in the eTPU include
separating the input and output signal, providing two action units per channel each with an input capture
and output compare, and providing a number of operating modes that combine the matches and compares
for complex logic interface to the pins.
A block diagram of the eTPU Channel Logic is shown in
Figure 1
To understand this diagram, it is useful
to consider the several subsystems separately.
2.1
Timer/Counter Registers
There are two timer counter registers in the eTPU that are available to all channels. These are the bases for
all captures and matches in the action units. There are some differences in the manner in which they are
driven. TCR1 can be derived from the system clock through a prescaler or can be driven from an external
source through the TCRCLK pin or from an external server through the STAC bus. Typically TCR1 is
derived from the system clock.
TCR2 can effectively be driven by the same sources as TCR1, plus it can be driven by special Angle Clock
logic in the eTPU. In this mode, the TCR2 tracks the position of a rotating wheel such as might be found
on an automotive engine or a motor shaft encoder. In examples below, the TCR2 value is often referred to
as the
angle
.
The TCRs are 24 bits wide. In counting mode, they roll over from 0xFFFFFF to 0x000000 and continue
counting. In angle mode, the counter can be set to reset to zero periodically, corresponding to the
revolution of the wheel. The TCR counters may be written by eTPU software or frozen on execution of a
register write. The TCRs can be read but not written by the host.
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