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參數(shù)資料
| 型號： | AN2635 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | On-Chip FLASH Programming Routines |
| 中文描述： | 片上閃存編程例程 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 150K |
| 代理商： | AN2635 |
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How to Use the Routines
On-Chip FLASH Programming Routines, Rev. 4
Freescale Semiconductor
11
Example 4: Send-Out Option
Example 4 shows how to use the send-out option:
RDVRRNG equ $0384 ;LB8 RDVRRNG jump address
bclr 0,DDRA ;Configure Port A bit 0 as an input
bclr 0,PTA ;Initialize data bit to zero PTA0=0
ldhx #$C025 ;Load last address of range to
sthx LADDR ; LADDR
ldhx #$C010 ;Load beginning address of range
; to H:X
clra ;A=0 to select send-out option
jsr RDVRRNG ;Call RDVRRNG routine
; A contains a checksum value
PRGRNGE
PRGRNGE is used to program a range of FLASH locations with data loaded into the DATA array. The
range must be less-than or equal-to 32 bytes. All bytes that will be programmed must be in the same row.
Programming data is passed to PRGRNGE in the DATA array. The size of the DATA array must match
the size of a specified programming range. This routine supports an internal operating frequency between
1.0 MHz and 8.4 MHz.
For this split-gate FLASH, the programming algorithm requires a programming time (t
prog
) between 30
μ
s
and 40
μ
s. (Refer to the FLASH memory section in the device data sheet.)
Table 4
shows how t
prog
is
adjusted by a CPUSPD value in this routine. The CPUSPD value is the nearest integer of f
op
(in MHz)
multiplied by 4. For example, if f
op
is 2.4576 MHz, the CPUSPD value is 10 ($0A). If f
op
is 8.0 MHz, the
CPUSPD value is 32 ($20).
In PRGRNGE, the high programming voltage time is enabled for less than 125
μ
s when programming a
single byte at any operating bus frequency between 1.0 MHz and 8.4 MHz. Therefore, even when a row
is programmed by 32 separate single-byte programming operations, the cumulative high voltage
programming time is less than the maximum t
HV
(4 ms). The t
HV
is defined as the cumulative high voltage
programming time to the same row before the next erase. For more information, refer to the memory
characteristics in the electrical specifications section of the device data sheet.
This routine does not confirm that all bytes in the specified range are erased prior to programming. Nor
does this routine perform a verification after programming, so there is no return confirmation that
programming was successful. To program data successfully, the user software is responsible for these
Table 4. t
prog
vs. Bus Frequency
Operating Bus Freq. (f
op
)
1.0 MHz
≤
f
Bus
<
1.125 MHz
1.125 MHz
≤
f
Bus
≤
8.4 MHz
CPUSPD
4
5 to 34
t
prog(Cycles)
38
8 x CPUSPD + 5
t
prog
Case 1
Case 2
33.8
μ
s
<
t
prog
≤
38.0
μ
s
32.1
μ
s
≤
t
prog
≤
40.0
μ
s
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