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參數(shù)資料
| 型號： | AN1816 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | USING THE HC912B32 TO IMPLEMENT THE DISTRIBUTED SYSTEMS INTERFACE (DSI) PROTOCOL |
| 中文描述： | 使用本HC912B32為實施分布式系統(tǒng)接口（DSI）協(xié)議 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 332K |
| 代理商： | AN1816 |
AN1816
14
Application Note
DSIxH:DSIxL register pair for 16-bit messages; DSIxL for 8-bit. The
transfer begins once DSIxL has been written to. Similarly, responses
from the slave nodes are written into these registers. The DSISTAT
register provides status information and should be checked before and
after transfers. It contains an error flag, ERx, which indicates if the
master received an invalid CRC value. Also, transmit and receive status
information, TFEx, TFNFx and RFNEx, is available through this register.
The DSIxCTRL register is written to before data is sent over the DSI bus.
This register is used to specify an additional divider between the SCLK
input and the bit timing circuitry, CDIVx[B:A], as well as defining the
DSI1H
- Data Access for DSI/D Channel 1(high byte)
address -
010
Bit 7
6
5
4
3
2
1
Bit 0
Bit-15
Bit-14
Bit-13
Bit-12
Bit-11
Bit-10
Bit-9
Bit-8
High
DSI1L
- Data Access for DSI/D Channel 1(low byte)
address -
011
Bit 7
6
5
4
3
2
1
Bit 0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Low
DSISTAT
- DSI Status Register
address -
100
Bit 7
6
5
4
3
2
1
Bit 0
ER1
TFE1
TFNF1
RFNE1
ER0
TFE0
TFNF0
RFNE0
DSI0CTRL
- DSI Channel 0 Control Register
address -
101
Bit 7
6
5
4
3
2
1
Bit 0
CDIV0B
CDIV0A
DLY0B
DLY0A
RIE0
TIE0
0
MS0
DSI1CTRL
- DSI Channel 1 Control Register
address -
110
Bit 7
6
5
4
3
2
1
Bit 0
CDIV1B
CDIV1A
DLY1B
DLY1A
RIE1
TIE1
0
MS1
DSIENABL
address -
111
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
EN1
EN0
Table 2 DSI Registers (Continued)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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