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參數(shù)資料
| 型號： | AN1816 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | USING THE HC912B32 TO IMPLEMENT THE DISTRIBUTED SYSTEMS INTERFACE (DSI) PROTOCOL |
| 中文描述： | 使用本HC912B32為實施分布式系統(tǒng)接口（DSI）協(xié)議 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 332K |
| 代理商： | AN1816 |
AN1816
12
Application Note
Figure 11 Slave Board Schematic
shows the schematic for the slave
board. A benefit of the DSI architecture is that the slave board requires
only a few additional components. Zener diodes are used to protect
against ESD damage to signals BusIn and BusOut. C1 (filt_cap)
supplies the power to the BEM IC during signalling. When laying out the
slave board, the pads for capacitor, C1 were enlarged so that they could
accommodate various values of capacitor from 1
depending on what was required of the evaluation system. For the slave
node described in this Application Note a 1
being capable of storing enough charge to power the BEM IC during
signalling. All components were positioned where signal trace lengths
could be kept to a minimum and signal traces were made as wide as
possible. Also, analogue and digital grounds were connected together
as close to the BEM IC as possible.
μ
F up to 4.7
μ
F
μ
F capacitor was selected as
SOFTWARE DESIGN
The initialisation software can be divided into 3 sections - initialisation of
the PWM and SPI, initialisation of the MC68HC55 SPI peripheral’s
registers and initialisation of the slave nodes.
Initialisation of
the PWM and
SPI
The PWM on the HC912B32 provides the system clock (SCLK) for the
MC68HC55 SPI Peripheral. The system software must initialise the
PWM so that it supplies a clock signal to the MC68HC55 SPI Peripheral
with the appropriate duty cycle and period. An example of possible C
source code that can be used to perform this set-up is shown in function
InitPWM in
Appendix 1 - Source Code
. The PWM registers, in this
example, are set up to generate a clock signal with a duty cycle of 50%
and a period of 3.5
μ
s (frequency of 285kHz).
The SPI is set up such that the slave select (SS) pin on the HC912B32
(connected to chip select (CS) on the MC68HC55 SPI Peripheral) is
configured as a general purpose I/O pin allowing the software to control
it. This is necessary for SPI Burst Transfers, thus enabling the
HC912B32 to communicate with the slave nodes via the MC68HC55
and the MC33790.
Figure 12 SPI Burst Transfer Example
shows an
example of an SPI burst transfer.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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