參數(shù)資料
型號(hào)： AN1816
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： USING THE HC912B32 TO IMPLEMENT THE DISTRIBUTED SYSTEMS INTERFACE (DSI) PROTOCOL
中文描述： 使用本HC912B32為實(shí)施分布式系統(tǒng)接口（DSI）協(xié)議
文件頁(yè)數(shù)： 10/24頁(yè)
文件大小： 332K
代理商： AN1816
AN1816
10
Application Note
Schematics and
Layout
Considerations -
Master Board
Figure 10 Master Board Schematic
Figure 10 Master Board Schematic
shows the schematic for the master
board. The board was based on an existing HC912B32 Evaluation
Board (EVB) with the addition of the required DSI circuitry. The
HC912B32 EVB circuitry allows the board to be used to evaluate
prototype hardware and software. When laying out the DSI circuitry on
the master board, the bus traces out of the MC33790 were made as wide
as possible to deal with the presence of the higher voltage (the DSI bus
maximum idle voltage is 25V). All components were positioned where
clock and bus trace lengths could be kept to a minimum. 0.1
capacitors were used to filter the bus supply voltage and to decouple the
power supplies to the MC68HC55 and MC33790. These capacitors were
placed as close to the ICs as possible.
μ
F
SCLK
CLK
DI
DO
CS
RESET
INT
Gnd
Vdd
DSI0F
DSI0S
DSI0R
n.c.
DSI1F
DSI1S
DSI1R
DSI0F
DSI0S
DSI0R
DSI1F
DSI1S
DSI1R
n.c.
CPCAP
Vdd
Gnd0
DSI0O
Vsup
DSI1O
Gnd1
n.c.
n.c.
C22
0.1
μ
F
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
U9 - DSID
U11 - DSIP
W19 - TP2
DSI Ch.1 Rx Data
DSI Ch.0 Rx Data
W17 - TP1
C23
0.1
μ
F
Vdd
C24
0.1
μ
F
Vdd
W18
R15
100
PP0/PW0
PS6/SCK
PS5/MOSI
PS4/MISO
PS7/SS
PS3
PE1/IRQ
1
1
C26
10
μ
F
+
W21
n.c.
no pin
25v
Gnd
Bus Power
W20
W22
D
D
M
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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