- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄364677 > AN-01 Clock System Design PDF資料下載
參數(shù)資料
| 型號： | AN-01 |
| 英文描述： | Clock System Design |
| 中文描述： | 時鐘系統(tǒng)設(shè)計 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 97K |
| 代理商： | AN-01 |
5
APPLICATION NOTE
AN-01
Micrel
Designing With Micrel-Synergy PECL Clock
Distribution Chips
Designing clock distribution systems with the Micrel-
Synergy PECL series of clock chips is straightforward, as
shown above. The simplicity of system design is a result of
several advantages of the PECL/TTL clock distribution
system approach. The elements of clock skew in the PECL/
TTL approach are typically much lower and more predictable
than in TTL-only designs.
The delay through a PECL chip is typically 1/5 to 1/10
the corresponding delay through a TTL chip. The SY10E111
PECL clock distributor shown in Figure 3 has a propagation
delay of 0.63ns compared to the TTL 74FCT244D at 3.8ns.
Lower propagation delay also means lower skew. The PECL
SY10E111 has very low on-chip skew (0.05ns) and relatively
low chip-to-chip skew (0.20ns) as compared to TTL buffer
chips which have typical skews of 1.0ns and 2.5ns,
respectively. The speed of PECL technology also applies to
the SY10H842 PECL/TTL clock driver. It has a maximum
propagation delay of 3.5ns, a maximum output-to-output
skew of 0.3ns, and a maximum part-to-part skew of only
0.5ns.
Differential PECL signals minimize the propagation delay
per inch of trace between the SY10E111 clock distributor
and the SY10H842 PECL/TTL clock drivers. The delay per
inch of trace on a PC board is 0.144ns/inch for G-10 glass
epoxy boards with a dielectric constant of 4.7. This
represents the minimum propagation delay per inch of trace.
Adding capacitance to the trace increases this delay per
inch value. Reducing the transmission line impedance of
the traces reduces the effect of this capacitance. PECL
chips such as the SY10E111 are designed to drive low
impedance, 50 ohm transmission lines. This low impedance
minimizes the effect of the SY10H842 PECL input
capacitance at the receiving end of the trace, which keeps
the propagation delay per inch of the transmission line low.
This combination allows the SY10E111 and SY10H842
combination to achieve a 0.15ns/inch delay.
Differential PECL signals also provide high noise immunity
compared to single-ended TTL signals. Crosstalk, ground
and power noises tend to affect both PECL signals in the
same way. The result is common mode noise on the signal
pair. This common mode noise is rejected by the differential
PECL input. The result is a clean signal as seen by the
PECL inputs. This means no clock jitter due to noise,
preservation of clock duty cycle, and no problem with V
CC
variations from one part of the board to another. PECL
signals for clock distribution also mean low EM radiation
because of the lower voltage swing and the fact that voltages
and currents of differential PECL transmission lines cancel
each other for minimum radiation.
Differential PECL signals provide a third, unique capability:
low skew inverted clocks. By simply exchanging the PECL
signals to a selected PECL-to-TTL clock driver, the output
clock signals output from that driver are inverted with respect
to other clocks in the system.
With these advantages in mind, the following is a set of
PECL/TTL clock system design recommendations:
Use the PECL SY10E111-to-SY10H842 lines for clock
routing for minimum delay and noise.
Use 50 ohm stripline (internal) traces for the PECL
lines. This gives 50 ohm lines in small size.
Make the PECL traces equal length for minimum skew.
Each inch difference is 0.15ns of skew.
Put the PECL/TTL converters near their loads: keep
the TTL traces short for low noise and delay.
Use one TTL driver per load and keep the loads as
equal as possible for minimum skew and noise.
PECL Clock Distribution Line Termination
The PECL lines from the SY10E111 to the SY10H842s
are transmission lines for traces longer than one inch. These
traces must be terminated at the SY10H842 end in the
characteristic impedance of the transmission line; otherwise,
there will be signal reflection and noise which can distort
the clock signal. The SY10E111 is designed to drive 50
transmission lines. One can design printed circuit traces to
be 50
transmission lines by properly sizing the width of
the trace (see Appendix 1). There remains the requirement
of terminating each of the pair of lines in its 50
impedance.
One can terminate the differential PECL signals with 50
resistors to a terminating voltage of 3V (i.e., 2.0V below
V
CC)
. This requires a separate terminating voltage power
supply. A simpler method is to use an RC network, as
shown in Figure 6. The RC network of Figure 6 takes
advantage of the fact that the signals are differential and
always opposite in phase. The two termination resistors, Rt,
are connected to a common bias resistor, Rb. The bias
resistor provides the current that would normally be supplied
by a 3.0V terminating voltage power supply.
The correct size for the Rb bias resistor is 107
; a 110
resistor will work. The decoupling capacitor, Ct, keeps the
terminating voltage constant while the signals are switching
so that each line sees a 50
terminating impedance. The
RC time constant of Ct and the terminating resistors would
be 10 times the round trip delay of the longest transmission
Figure 6. PECL Resistor Termination
PECL
PECL
V
CC
Rt
50
Rt
50
Rb
110
Ct
10nF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AN-03 | SONET OC-12 Jitter Measurement |
| AN-04 | SONET OC-3 Jitter Measurement |
| AN-05 | SY69952 in an OC-3 Transmission System |
| AN-06 | SY89429A Frequency Synthesis |
| AN-15 | TOPSwitch Power Supply Design Techniques for EMI & Safety |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AN-010 | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:Reflow Soldering Guidelines for RoHS* Compliant E-Series Surface Mount Components |
| AN0116 | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:8 Channel Power MOSFET Array Monolithic N-channel Enchancement Mode |
| AN0116NA | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:8 Channel Power MOSFET Array Monolithic N-channel Enchancement Mode |
| AN0116NB | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:8 Channel Power MOSFET Array Monolithic N-channel Enchancement Mode |
| AN0116ND | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:8 Channel Power MOSFET Array Monolithic N-channel Enchancement Mode |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。