- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄364677 > AN-01 Clock System Design PDF資料下載
參數(shù)資料
| 型號(hào)： | AN-01 |
| 英文描述： | Clock System Design |
| 中文描述： | 時(shí)鐘系統(tǒng)設(shè)計(jì) |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 97K |
| 代理商： | AN-01 |
4
APPLICATION NOTE
AN-01
Micrel
The total clock skew for the system is the sum of the
skews of the various elements. The total skew in this
example is 1.00ns. Note that 0.30ns of this delay is due to
trace length differences of 3/4 inch on the PECL and 3/4
inch on the TTL traces. Also, 0.15ns of skew is due to 5pF
difference in loading on the various outputs. These values
are affected by the system design and board layout. If these
differences could be cut in half, for example, the skew could
be cut by 0.23ns, reducing the total skew to 0.77ns. The
rule of thumb for maximum skew is 10% of a clock cycle.
For a 100MHz system, the maximum skew is 1ns. Utilizing
Micrel-Synergy's low skew SY10E111 and SY10H842 PECL
clock distribution system, this maximum skew requirement
can easily be met.
System Clock Skew Requirements
Now that we know how to calculate clock skew, we need
to know how to calculate the system clock skew
requirements (i.e., the system clock skew design budget).
Clock skew is the main design parameter in high-speed
clock systems. System timing determines clock skew
requirements. The system timing diagram of Figure 5 shows
the effect of clock skew. In this diagram, we have a data
source, such as the CPU, driving a receiver such as an I/O
device. The CPU puts data on the bus that is received and
clocked in by the I/O device. The CPU makes the data valid
on the bus for a set-up time, t
BS
, before the clock. The CPU
holds it valid for a hold time, t
BH
, after the clock. The I/O
device requires that data be present at its inputs for a set-
up time, t
IS
, before the clock, and that it be held valid for a
hold time, t
IH
, after the clock. The timing design margin is
the amount of excess time the data is valid before the
minimum required set-up time and after the minimum
required hold time. The design margin for data set-up is
(t
BS
–
t
IS
); for data hold, it is (t
BH
–
t
IH
).
Let us consider the case where the I/O device receives
an early version of the clock, called I/O Clock in Figure 5.
This clock is early with respect to the CPU clock, the source
of the data on the bus. The I/O device input set-up and hold
window is relative to its clock. In Figure 5, I/O Clock has
moved the I/O input set-up and hold window early enough
in the cycle that the data on the bus is not yet valid and its
input set-up requirements are violated. A similar situation
occurs if the I/O device clock is late. If the I/O clock is too
late, the I/O input hold requirement is violated.
Excessive clock skew violates input set-up or hold
requirements for control or data signals. The problem is
also relative. The clock at the receiver is early or late with
respect to the clock at the driver. In the case shown, the
CPU is driving an I/O device, and the I/O device clock is
early with respect to the CPU clock. If the I/O device is
driving the CPU on the next cycle, the CPU clock will be
late with respect to the I/O device.
The difference in timing between two clock signals is
called clock skew. The difference in time between the rising
edges of CPU Clock and I/O Clock in Figure 5 is the clock
skew, t
SKEW
. The maximum value of skew is determined by
the set-up time margin (t
BS
–
t
IS
) for I/O Clock arriving
early, to the hold time margin (t
BH
–
t
IH
) for I/O Clock arriving
late. Since clock skew is relative, all combinations of data
output set-up and hold and data input set-up and hold are
considered. The allowable clock skew is the minimum of
these combinations of set-up and hold margins.
Figure 5. Clock Skew Timing Diagram
VALID
t
BS
t
BH
VALID
t
IS
t
IH
VALID
t
SKEW
t
IS
t
IH
CPU CLOCK
BUS DATA
CPU INPUT WINDOW
I/O CLOCK
I/O INPUT WINDOW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AN-03 | SONET OC-12 Jitter Measurement |
| AN-04 | SONET OC-3 Jitter Measurement |
| AN-05 | SY69952 in an OC-3 Transmission System |
| AN-06 | SY89429A Frequency Synthesis |
| AN-15 | TOPSwitch Power Supply Design Techniques for EMI & Safety |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AN-010 | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:Reflow Soldering Guidelines for RoHS* Compliant E-Series Surface Mount Components |
| AN0116 | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:8 Channel Power MOSFET Array Monolithic N-channel Enchancement Mode |
| AN0116NA | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:8 Channel Power MOSFET Array Monolithic N-channel Enchancement Mode |
| AN0116NB | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:8 Channel Power MOSFET Array Monolithic N-channel Enchancement Mode |
| AN0116ND | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:8 Channel Power MOSFET Array Monolithic N-channel Enchancement Mode |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。