- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄364677 > AN-01 Clock System Design PDF資料下載
參數(shù)資料
| 型號(hào)： | AN-01 |
| 英文描述： | Clock System Design |
| 中文描述： | 時(shí)鐘系統(tǒng)設(shè)計(jì) |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 97K |
| 代理商： | AN-01 |
APPLICATION NOTE
AN-01
Introduction
Clock distribution is a significant design challenge for
systems operating above 25MHz. The Micrel-Synergy
Semiconductor PECL series of clock chips simplifies
designs by significantly reducing clock skew — the source
of most problems in high-speed clock distribution design.
This application brief examines the various aspects of
clock system design using a system design as an
example.
Figure 1 shows an example of such a high-speed
computer system with a clock subsystem. The system
consists of a 32-bit CPU with a memory control
subsystem, peripheral chips and a clock subsystem. The
clock subsystem drives the various clock pins of the
system. The clock subsystem consists of an ECL crystal
oscillator (Xtal), an SY10E111 PECL clock distributor,
and SY10H842 PECL-to-TTL clock drivers. The
SY10E111 PECL clock distributor generates the primary
clock signal and drives the SY10H842 PECL-to-TTL clock
drivers.
CLOCK SYSTEM DESIGN
Figure 1. A 32-Bit Microprocessor System
Differential PECL signals, such as those used by the
SY10E111 and SY10H842, have unique advantages for
clock distribution systems. Differential PECL signals
provide good noise rejection. Because they are differential
and have low swing, they minimize EM radiation from
the board; they can drive low impedance transmission
line traces for minimum trace delay; they have equal rise
and fall times which preserves the clock duty cycle; and,
by exchanging the inputs to the PECL-to-TTL converter,
one can obtain inverted clocks easily with minimum skew.
Synchronous digital systems — such as shown in
Figure 1 — use the concept of a single clock coordinating
the actions of all system components. In real systems,
the low-to-high controlling clock edges do not happen at
the same time. The difference in time between the rising
edge of one clock pin and another is called clock skew.
Clock skew is generated by differences in delay between
the clock oscillator and the clock pins. This delay is a
combination of the delay through different clock drivers
and the time required for the clock to propagate down
the PC board trace (known as trace delay).
Rev.: D
Issue Date:
Amendment: /0
June, 1998
SRAM
DRAM
ASIC
I/O
CPU
S
X
S
S
S
T
P
T
T
P
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AN-03 | SONET OC-12 Jitter Measurement |
| AN-04 | SONET OC-3 Jitter Measurement |
| AN-05 | SY69952 in an OC-3 Transmission System |
| AN-06 | SY89429A Frequency Synthesis |
| AN-15 | TOPSwitch Power Supply Design Techniques for EMI & Safety |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AN-010 | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:Reflow Soldering Guidelines for RoHS* Compliant E-Series Surface Mount Components |
| AN0116 | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:8 Channel Power MOSFET Array Monolithic N-channel Enchancement Mode |
| AN0116NA | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:8 Channel Power MOSFET Array Monolithic N-channel Enchancement Mode |
| AN0116NB | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:8 Channel Power MOSFET Array Monolithic N-channel Enchancement Mode |
| AN0116ND | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:8 Channel Power MOSFET Array Monolithic N-channel Enchancement Mode |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。