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| 型號(hào)： | AN-01 |
| 英文描述： | Clock System Design |
| 中文描述： | 時(shí)鐘系統(tǒng)設(shè)計(jì) |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大小： | 97K |
| 代理商： | AN-01 |
3
APPLICATION NOTE
AN-01
Micrel
Several variations of the SY10H842 are also available.
The SY10H841 is a 4-output part, similar to the SY10H842,
but has an input latch for holding the clock signal in a
specified state. The SY10H843 is similar to the SY10H842
but has a pair of input latches for both the data and enable
signals. It has a synchronous enable for stopping the clock
without glitches or short pulse effects. The SY10H641 is a
9-output PECL-to-TTL converter in a 28-pin PLCC package.
Note that all the PECL-to-TTL clock driver chips in a system
design must be of the same type for the specified package-
to-package skew specification to apply. All of the clock chips
are available with either 10K PECL (e.g. SY10E111) or
100K PECL (e.g. SY100E111) signal level compatibility.
Calculating Skew
Clock skew is defined as the difference in time between
the clock edges arriving at a pair of clock input pins. In a
perfect system, all clock signals arrive at all the various
clock input pins of the system at exactly the same time, and
the skew is zero. In real systems, the edges do not arrive at
exactly the same time and there is some skew. Clock skew
exists because of differences in the delay paths from the
master clock oscillator to the various clock input pins. Delay
accumulates along each clock path and the delays for the
various paths are not equal. The maximum clock skew for
the system is the difference in delay between the shortest
and longest delay paths.
We can calculate the skew for a system by calculating
the differences in delay along the clock paths. In the clock
system of Figure 1, each delay path consists of the following
elements:
Delay through the SY10E111
Trace delay from the SY10E111 to the SY10H842
Delay through the SY10H842
Output delay of the SY10H842 due to capacitive
loading
Trace delay from the SY10H842 to the clock input pin
IN
IN
EN
Q
0
Q
1
Q
2
Q
3
Delay Element
Skew
Value
SY10E111 Output-to-Output Skew, Max.
0.05
ns
Trace Delay, SY10E111-to-SY10H842,
3/4" Difference at 0.15ns/in
0.10
ns
SY10H842 Package-to-Package Skew, Max.
0.50
ns
Loading Delay, SY10H842,
5pF Difference at 1.5ns/50pF
0.15
ns
Trace Delay, SY10H842-to-Load,
3/4" Difference at 0.25ns/in
0.20
ns
Totals
1.00
ns
The delay from the master clock oscillator to the
SY10E111 does not contribute to clock skew because it is
exactly the same for all clock paths: all clocks share this
delay path element. The SY10E111 data sheet specifies
the maximum skew between outputs on the same chip to
be less than 0.05ns. Small clock systems such as this
example use a single SY10E111 which adds only 0.05ns to
the total skew. Large clock systems using one SY10E111
driving other SY10E111s have 0.05ns of skew for the first
SY10E111, plus 0.20ns of package-to-package skew for
each layer of SY10E111s.
Trace delay from the SY10E111 to the SY10H842 is
determined by the length of the clock trace on the printed
circuit board, the material of the board, and the capacitive
loading of the SY10H842 input. For glass epoxy printed
circuit cards, the unloaded trace delay is 0.144ns/inch. The
capacitive loading of the input pins of the SY10H842
increases this delay. A figure of 0.15ns/inch is used in this
example.
The skew for outputs within a single SY10H842 is 0.30ns;
however, this example uses more than one chip so the
chip-to-chip skew value of 0.50ns must be used.
The SY10H842 is specified with a 50pF load. Good design
practice dictates that each SY10H842 TTL output drive only
one load
—
typically between 5 and 10pF. The SY10H842
loading factor is 1.5ns per 50pF additional capacitance. If
the loads on the outputs differ by 5pF, a corresponding
skew of 0.15ns is introduced.
The final element of skew is trace delay from the
SY10H842 to the load (i.e., the clock input pin being driven).
The TTL trace is typically more heavily loaded than the
PECL lines from the SY10E111 to the SY10H842. This
means that the TTL trace delay per inch of trace is larger
than the 0.144ns/inch of unloaded traces. A typical number
is 0.25ns/inch. This number is used in the calculations, and
the traces are assumed to be from 1 1/4 inch to 2 inches
long from the SY10H842 to the various clock input pins.
Table 1. System Clock Skew Example
Figure 4. SY10H842 Block Diagram
The delay for the shortest and longest path for the system
shown in Figure 1 are given in Table 1.
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