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參數(shù)資料
| 型號： | AN-01 |
| 英文描述： | Clock System Design |
| 中文描述： | 時鐘系統(tǒng)設(shè)計 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 97K |
| 代理商： | AN-01 |
2
APPLICATION NOTE
AN-01
Micrel
SY10H842
SY10H842
IC
IC
IC
IC
IC
IC
IC
SY10E111
OSC
Printed Circuit Board
Figure 2. Clock Distribution Board Layout Example
Figure 3. SY10E111 Block Diagram
Figure 2 shows what a board layout of the system of
Figure 1 might look like. Note that the traces run in
serpentine patterns to keep the trace lengths from the
SY10E111 to the SY10H842s and from the SY10H842s
to their IC loads equal in length.
The PECL Clock Chips
Figures 3 and 4 show block diagrams of the SY10E111
and SY10H842 PECL clock chips, respectively. The
SY10E111 is a 1-in, 9-out PECL clock distributor chip. It
multiplies the single clock input from the crystal oscillator
into 9 copies for distribution to the SY10H842 chips. The
SY10E111 has very low output-to-output skew (0.05ns) and
low part-to-part skew (0.2ns). The SY10E111 is normally
driven by the master clock source
—
the crystal oscillator in
this case
—
and the SY10E111 outputs drive PECL-to-TTL
clock drivers such as the SY10H842. The SY10E111 can
also drive other SY10E111 chips. One can create large
clock systems with low skew by using the first SY10E111
chip to drive other SY10E111 chips. A single SY10E111
generates 9 PECL clock outputs and up to 36 TTL outputs
using SY10H842 PECL-to-TTL clock drivers. Two layers of
SY10E111s can generate up to 81 PECL clock outputs and
324 TTL outputs. The SY10E111 is available in a 28-pin
PLCC package. The PLCC package allows balanced lead
lengths for low skew, and the plastic package minimizes
propagation delay.
The SY10H842 is a 4-output PECL-to-TTL converter. The
SY10H842 has low output-to-output skew for outputs in the
same package (0.3ns) and for outputs in different packages
(0.5ns). It has flow-through style pinouts for ease of layout
and one TTL ground for each pair of outputs for low ground
bounce noise. It is supplied in a 16-pin, low-inductance
SOIC package.
EN
IN
IN
Q
0
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0
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1
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1
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2
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3
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4
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