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參數(shù)資料
| 型號： | AMMCL00XA |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | JT 3C 3#20 SKT RECP |
| 中文描述： | 2或4兆字節(jié)3.0伏，只有Flash微型卡 |
| 文件頁數(shù)： | 29/36頁 |
| 文件大?。?/td> | 172K |
| 代理商： | AMMCL00XA |
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AmMCL00XA
29
P R E L I M I NA R Y
AIS MEMORY MAP
The AIS (Attribute Information Structure) is an area of
memory used for storing information about the config-
uration of the Miniature Card. The AIS is recommended
to be stored in the first sector of the first device of the
Flash array. As this area is not explicitly protected, the
AIS information must be reloaded onto the card in the
event that the information is erased.
The AIS has five unique information areas:
1. Identification Data: This data includes Manufacturer
information (Manufacturer and card name).
2. Compatibility Data: This data specifies basic infor-
mation about the card (memory size, access time,
memory type, power, etc.)
3. Burst Data (not applicable)
4. DRAM Data (not applicable)
5. Reserved Data: This data area is reserved for future use.
The AIS supports up to four different memory technol-
ogies on a card. Some of the information areas are
repeated in the memory map in order to specify dif-
ferent technologies (see Table 12). The Technology
Count field in the Identification Data section defines the
number of different technologies on a card. The first
memory technology is defined in the AIS memory map
from address 40H through 7FH. The second memory
technology is defined from 80H through BFH. The third
memory technology is defined from C0H to DFH. The
fourth memory technology is defined from E0H to FFH.
The AIS is stored as bytes within the 16-bit Miniature
Card data word. The even byte D0–D7 stores the AIS
data, and the odd byte D8–D15 is reserved by the card
manufacturer for manufacturing information.
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. D7 is the complement of the data written to the device.
4. D
OUT
is the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
6. These waveforms are for the x16 mode.
21138E-13
Figure 12.
Alternate CE# Controlled Write Operation Timings
t
WH
t
WS
OE#
CE#
WE#
V
CC
t
DS
Data
t
AH
Addresses
t
DH
t
CP
PD
DQ7#
D
OUT
t
EHEH3_or_4
t
WC
t
AS
t
CPH
t
VCS
XXXXh
PA
PA
Data# Polling
A0h
t
GHEL
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