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參數(shù)資料
| 型號： | AMMCL00XA |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | JT 3C 3#20 SKT RECP |
| 中文描述： | 2或4兆字節(jié)3.0伏，只有Flash微型卡 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大小： | 172K |
| 代理商： | AMMCL00XA |
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AmMCL00XA
11
P R E L I M I NA R Y
Table 4.
Miniature Card Read/Write Modes
Notes:
1. Unlisted access combinations are invalid and may return unexpected results.
2. X indicates a don’t care value.
Erase Operations
The AMD Flash Miniature Card is organized as an
array of individual devices. Each Am29LV081 device
contains sixteen 64 KByte sectors, for a total of 1 Mbyte
of memory space per device.
Flash technology allows any logical “1” data bit to be pro-
grammed to a logical “0”. The only way to reset bits to a
logical “1” is to erase that entire memory sector or
memory device. Once a memory sector or memory
device is erased, any address location may be pro-
grammed. Two or more devices may be erased concur-
rently when additional I
CC
current is supplied to the card.
However, erasing more than two devices concurrently is
not typical in battery-powered applications, but may take
place during procedures such as card testing.
Erase operations can be performed in several ways:
I
Erase a single sector or multiple sectors in a device
I
Erase a sector pair
I
Erase multiple device pairs*
I
Erase the entire card*
* This operation is only feasible in solutions capable of
supplying more than the specified miniature card
supply current requirement (150mA) per system. Each
AMD Flash memory
device pair
can accept a
maximum of 120mA supply current.
The common memory space data contents are altered
in a similar manner to writing to individual Flash
memory devices. An on-card address decoder acti-
vates the appropriate Flash device in the memory
array. Each device internally latches address and data
during write cycles. Refer to Table 4.
Standby Mode
The AMD flash devices are designed to accommodate
low standby power consumption. In order to achieve
standby mode, the CE# line must be deselected. In
addition, while in the standby mode, data I/O pins
remain in the high impedance state independent of the
voltage level applied to the OE# input. See the DC
Characteristics section for more details on Standby
Modes.
Deselecting CE# (CE# and RESET# = V
CC
±
0.3 V)
puts the device into the I
CC3
standby mode. If the
device is deselected during an Embedded Algorithm
operation, it continues to draw active power (I
CC2
) prior
to entering the standby mode, until the operation is
complete. When the device is again selected (CE# =
V
IL
), active operations occur in accordance with the
AC timing specifications.
Automatic Sleep Mode
Advanced power management features such as the
automatic sleep mode minimize Flash device energy
consumption. This is extremely important in bat-
tery-powered applications. The AMD memory devices
automatically enable the low-power, automatic sleep
mode when addresses remain stable for 300 ns. Auto-
matic sleep mode is independent of the CE#, WE#, and
OE# control signals. Typical sleep mode current draw
from each device is < 1
μ
A. Standard address access
timings provide new data when addresses are
Function
CEH#
CEL#
WE#
OE#
D8–D15
D0–D7
Read Mode
Word Access
L
L
H
L
High Byte Data
Low Byte Data
Low Byte Access
H
L
H
L
High-Z
Low Byte Data
High Byte Access
L
H
H
L
High Byte Data
High-Z
Write Mode
Word Access
L
L
L
H
High Byte Data
Low Byte Data
Low Byte Access
H
L
L
H
High-Z
Low Byte Data
High Byte Access
L
H
L
H
High Byte Data
High-Z
Standby Mode
Standby
H
H
X
X
High-Z
High-Z
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