參數(shù)資料
型號: AMMCL00XA
廠商: Advanced Micro Devices, Inc.
英文描述: JT 3C 3#20 SKT RECP
中文描述: 2或4兆字節(jié)3.0伏,只有Flash微型卡
文件頁數(shù): 28/36頁
文件大小: 172K
代理商: AMMCL00XA
28
AmMCL00XA
P R E L I M I NA R Y
AC CHARACTERISTICS-ALTERNATE CE# CONTROLLED WRITES
Write/Erase/Program Operations
Notes:
1. Rise/fall time
10 ns.
2. Maximum specification not needed due to the internal stop timer that will stop any erase or write operation that exceed the
device specification.
3. Card Enable Controlled Programming:
Flash Programming is controlled by the valid combination of the Card Enable (CE1#, CE2#) and Write Enable (WE#) signals.
For systems that use the Card Enable signal(s) to define the write pulse width, all setup, hold, and inactive write enable timing
should be measured relative to the Card Enable signal(s).
4. Under worst case condition of 90
°
C, Vcc = 2.7 V, 100,000 cycles. Excludes system level overhead, the time required to
execute the four bus cycle command necessary to program each byte.
Parameter Symbols
Parameter Description
-150
Unit
JEDEC
Standard
t
AVAV
t
WC
Write Cycle Time
Min
150
ns
t
AVEL
t
AS
Address Setup Time
Min
10
ns
t
ELAX
t
AH
Address Hold Time
Min
50
ns
t
DVEH
t
DS
Data Setup Time
Min
50
ns
t
EHDX
t
DH
Data Hold Time
Min
0
ns
t
GLDV
t
OEH
Output Enable Hold Time for Embedded Algorithm
Min
10
ns
t
GHEL
Read Recovery Time before Write
Min
0
μ
s
t
WLEL
t
WS
WE# Setup Time before CE#
Min
0
ns
t
EHWH
t
WH
WE# Hold Time
Min
0
ns
t
ELEH
t
CP
CE# Pulse Width
Min
50
ns
t
EHEL
t
CPH
CE# Pulse Width HIGH (Note 3)
Min
20
ns
t
EHEH3
Embedded Programming Operation (Notes 3,4)
Typ
9
Max
300
μ
s
t
EHEH4
Embedded Erase Operation for each 64K byte Memory
Sector (Notes 1, 2)
Typ
1.5
Max
15
s
t
VCS
V
CC
Setup Time to Write Enable LOW
Min
50
μ
s
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