參數(shù)資料
型號(hào)： AMMCL00XA
廠商： Advanced Micro Devices, Inc.
英文描述： JT 3C 3#20 SKT RECP
中文描述： 2或4兆字節(jié)3.0伏，只有Flash微型卡
文件頁(yè)數(shù)： 10/36頁(yè)
文件大?。?/td> 172K
代理商： AMMCL00XA
10
AmMCL00XA
P R E L I M I NA R Y
Figure 3.
Write Protect Switch
(Card Right Side View)
In addition to card-level data protection, AMD Flash
Miniature Cards offer several device-level data protec-
tion features.
Device-Level Data Protection
AMD Flash memory devices offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power tran-
sitions. During power up, each device automatically
resets the internal state machine to the read mode. The
control register architecture allows alteration of the
memory contents only occurs after successful comple-
tion of specific multi-bus cycle command sequences.
AMD Flash memory devices also incorporates the fol-
lowing features to prevent inadvertent write cycles
resulting from V
CC
power-up and power-down transi-
tions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up
and power-down, the AMD memory devices in the Min-
iature Card lock out write cycles for V
CC
< V
LKO
(see
“DC Characteristics” on page 22 for voltages). When
V
CC
< V
LKO
, the command register is disabled, all
internal program/erase circuits are disabled, and the
device resets to the read mode. The memory devices
ignore all writes until V
CC
> V
LKO
. The user must
ensure that the control pins are in the correct logical
state when V
CC
> V
LKO
to prevent unintentional writes.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#,
or WE# will neither initiate a write cycle nor change the
command registers.
Logical Inhibit
Writing is inhibited by holding any one of OE# = V
IL
,
CE# = V
IH
, or WE# = V
IH
. To initiate a write cycle CE#
and WE# must be a logical zero while OE# is a logical
one.
Power-Up Write Inhibit
Power-up of the device with CE# = WE# = V
IL
and OE#
= V
IH
will not accept commands on the rising edge of
WE#. The internal state machine is automatically reset
to the read mode on power-up.
Read Mode
Two Card Enable (CE#) pins are available on the
memory card. Both CE# pins must be active low for
word-wide read accesses. Only one CE# is required for
byte-wide accesses. The CE# pins select and deter-
mine when to apply power to the high-byte and
low-byte memory devices. The Output Enable (OE#)
controls gating accessed data from the memory device
outputs. Refer to Table 4.
The Miniature Card automatically powers up in the
read/reset state. In this case, a command sequence is
not required to read data. Standard microprocessor
read cycles will retrieve array data. This default state
ensures that no spurious alteration of the memory
content occurs during the power transition. Refer to the
AC Read Characteristics and Waveforms for the spe-
cific timing parameters.
Output Disable
Data outputs from the card are disabled when OE# is
at a logic-high level. Under this condition, outputs are
in the high-impedance state.
Write Enabled
Write Disabled
21138E-1
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