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參數(shù)資料
| 型號(hào)： | AM79C976 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| 中文描述： | PCnet -專業(yè)⑩個(gè)10/100Mbps PCI以太網(wǎng)控制器 |
| 文件頁(yè)數(shù)： | 66/309頁(yè) |
| 文件大?。?/td> | 2070K |
| 代理商： | AM79C976 |
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66
Am79C976
8/01/00
P R E L I M I N A R Y
will stop advancing through the ring entries and begin
periodic polling of this entry. When the STP bit is found
to be true, and the descriptor that contains this setting
is owned by the Am79C976 controller, then the
Am79C976 controller will stop advancing through the
ring entries, store the descriptor information that it has
just read, and wait for the next receive to arrive.
This behavior allows the host software to pre-assign
buffer space in such a manner that the
header
portion
of a receive packet will always be written to a particular
memory area, and the
data
portion of a receive packet
will always be written to a separate memory area. The
interrupt is generated when the
header
bytes have
been written to the
header
memory area.
Software Interrupt Timer
The Am79C976 controller is equipped with a software
programmable free-running interrupt timer. The timer is
constantly running and will generate an interrupt STINT
(CSR 7, bit 11) when STINITE (CSR 7, bit 10) is set to
1. After generating the interrupt, the software timer will
load the value stored in STVAL and restart. The timer
value STVAL (BCR31, bits 15-0) is interpreted as an
unsigned number with a resolution of 10.24μs. For in-
stance, a value of 98 (62h) corresponds to 1.0 ms. The
default value of STVAL is FFFFh which corresponds to
0.671 seconds. A write to STVAL restarts the timer with
the new contents of STVAL.
Media Access Control
The Media Access Control (MAC) engine incorporates
the essential protocol requirements for operation of an
Ethernet/IEEE 802.3-compliant node and provides the
interface between the FIFO subsystem and the MII.
This section describes operation of the MAC engine
when operating in half-duplex mode. The operation of
the device in full-duplex mode is described in the sec-
tion titled
Full-Duplex Operation
.
The MAC engine is fully compliant to Section 4 of IEEE
Std 802.3, 1998 Edition.
The MAC engine provides programmable enhanced
features designed to minimize host supervision, bus
utilization, and pre- or post-message processing.
These features include the ability to disable retries after
a collision, dynamic FCS generation on a frame-by-
frame basis, automatic pad field insertion and deletion
to enforce minimum frame size attributes, automatic re-
transmission without reloading the FIFO, and auto-
matic deletion of collision fragments. The MAC also
provides a mechanism for automatically inserting, de-
leting, and modifying IEEE 802.3ac VLAN tags.
The two primary attributes of the MAC engine are:
I
—
Framing (frame boundary delimitation, frame
synchronization)
—
Addressing (source and destination address
handling)
—
Error detection (physical medium transmission
errors)
I
Media access management
—
Medium allocation (collision avoidance, except
in full-duplex operation)
—
Contention resolution (collision handling, except
in full-duplex operation)
!(#*%('
The MAC engine provides minimum frame size en-
forcement for transmit and receive frames. When
APAD_XMT (CSR4, bit 11) is set to 1, transmit mes-
sages will be padded with sufficient bytes (containing
00h) to ensure that the receiving station will observe an
information field (destination address, source address,
length/type, data, and FCS) of 64 bytes. When
ASTRP_RCV (CSR4, bit 10) is set to 1, the receiver will
automatically strip pad bytes from the received mes-
sage by observing the value in the length field and by
stripping excess bytes if this value is below the mini-
mum data size (46 bytes). Both features can be inde-
pendently over-ridden to allow illegally short (less than
64 bytes of frame data) messages to be transmitted
and/or received. The use of this feature reduces bus
utilization because the pad bytes are not transferred
into or out of main memory.
The MAC engine will autonomously handle the con-
struction of the transmit frame. Once the transmit FIFO
has been filled to the predetermined threshold (set by
XMTSP in CSR80) and access to the channel is cur-
rently permitted, the MAC engine will commence the
7-byte preamble sequence (10101010b, where first bit
transmitted is a 1). The MAC engine will subsequently
append the Start Frame Delimiter (SFD) byte
(10101011b) followed by the serialized data from the
transmit FIFO. Once the data has been transmitted, the
MAC engine will append the FCS (most significant bit
first) which was computed on the entire data portion of
the frame. The data portion of the frame consists of
destination address, source address, length/type, and
frame data. The user is responsible for the correct or-
dering and content in each of these fields in the frame.
The MAC does not use the content in the length/type
field unless APAD_XMT (CSR4, bit 11) is set and the
data portion of the frame is shorter than 60 bytes.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C976KIW | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| AM79C976KCW | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| AM79C978AKCW | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978AVCW | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978 | Single-Chip 1/10 Mbps PCI Home Networking Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C976KC | 制造商:Rochester Electronics LLC 功能描述:METRIC PLASTIC QUAD-RING - Bulk |
| AM79C976KCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| AM79C976KD | 制造商:Advanced Micro Devices 功能描述:ETHERNET:MEDIA ACCESS CONTROLLER (MAC) |
| AM79C976KF | 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP 制造商:AMD (Advanced Micro Devices) 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP |
| AM79C976KI | 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP 制造商:AMD (Advanced Micro Devices) 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP |
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