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參數(shù)資料
| 型號： | AM79C975 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | PCnet⑩快速三單芯片10/100 Mbps的PCI以太網(wǎng)控制器集成PHY |
| 文件頁數(shù)： | 285/304頁 |
| 文件大?。?/td> | 2092K |
| 代理商： | AM79C975 |
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Am79C973/Am79C975
285
P R E L I M I N A R Y
Outline of LAPP Flow
This section gives a suggested outline for a driver that
utilizes the LAPP feature of the Am79C973 controller.
Note:
The labels in the following text are used as ref-
erences in the timeline diagram that follows (Figure
B-1).
Setup
The driver should set up descriptors in groups of three,
with the OWN and STP bits of each set of three de-
scriptors to read as follows: 11b, 10b, 00b.
An option bit (LAPPEN) exists in CSR3, bit position 5;
the software should set this bit. When set, the LAPPEN
bit directs the Am79C973 controller to generate an IN-
TERRUPT when STP has been written to a receive de-
scriptor by the Am79C973 controller.
Flow
The Am79C973 controller polls the current receive de-
scriptor at some point in time before a message arrives.
The Am79C973 controller determines that this receive
buffer is OWNed by the Am79C973 controller and it
stores the descriptor information to be used when a
message does arrive.
N0
Frame preamble appears on the wire, followed
by SFD and destination address.
N1
The 64th byte of frame data arrives from the
wire. This causes the Am79C973 controller to
begin frame data DMA operations to the first
buffer.
C0
When the 64th byte of the message arrives,
the Am79C973 controller performs a looka-
head operation to the next receive descriptor.
This descriptor should be owned by the
Am79C973 controller.
C1
The Am79C973 controller intermittently re-
quests the bus to transfer frame data to the first
buffer as it arrives on the wire.
S1
The driver remains idle.
C2
When the Am79C973 controller has com-
pletely filled the first buffer, it writes status to
the first descriptor.
C3
When the first descriptor for the frame has
been written, changing ownership from the
Am79C973 controller to the CPU, the
Am79C973 controller will generate an SRP IN-
TERRUPT. (This interrupt appears as a RINT
interrupt in CSR0).
S1
The SRP INTERRUPT causes the CPU to
switch tasks to allow the Am79C973 control-
ler
’
s driver to run.
C4
During the CPU interrupt-generated task
switching, the Am79C973 controller is per-
forming a lookahead operation to the third de-
scriptor. At this point in time, the third
descriptor is owned by the CPU.
Note:
Even though the third buffer is not owned by the
Am79C973 controller, existing AMD Ethernet control-
lers will continue to perform data DMA into the buffer
space that the controller already owns (i.e., buffer num-
ber 2). The controller does not know if buffer space in
buffer number 2 will be sufficient or not for this frame,
but it has no way to tell except by trying to move the en-
tire message into that space. Only when the message
does not fit will it signal a buffer error condition--there is
no need to panic at this point that it discovers that it
does not yet own descriptor number 3.
S2
The first task of the drivers interrupt service
routing is to collect the header information
from the Am79C973 controller
’
s first buffer and
pass it to the application.
S3
The application will return an application buffer
pointer to the driver. The driver will add an off-
set to the application data buffer pointer, since
the Am79C973 controller will be placing the
first portion of the message into the first and
second buffers. (the modified application data
buffer pointer will only be directly used by the
Am79C973 controller when it reaches the third
buffer.) The driver will place the modified data
buffer pointer into the final descriptor of the
group (#3) and will grant ownership of this de-
scriptor to the Am79C973 controller.
C5
Interleaved with S2, S3, and S4 driver activity,
the Am79C973 controller will write frame data
to buffer number 2.
S4
The driver will next proceed to copy the con-
tents of the Am79C973 controller
’
s first buffer
to the beginning of the application space. This
copy will be to the exact (unmodified) buffer
pointer that was passed by the application.
S5
After copying all of the data from the first buffer
into the beginning of the application data
buffer, the driver will begin to poll the owner-
ship bit of the second descriptor. The driver is
waiting for the Am79C973 controller to finish
filling the second buffer.
C6
At this point, knowing that it had not previously
owned the third descriptor and knowing that
the current message has not ended (there is
more data in the FIFO), the Am79C973 con-
troller will make a last ditch lookahead to the
final (third) descriptor. This time the ownership
will be TRUE (i.e., the descriptor belongs tot he
controller), because the driver wrote the appli-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C973 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C975BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\W | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975BKDW | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
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