- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄366550 > AM79C975 (Advanced Micro Devices, Inc.) PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C975 |
| 廠(chǎng)商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | PCnet⑩快速三單芯片10/100 Mbps的PCI以太網(wǎng)控制器集成PHY |
| 文件頁(yè)數(shù)： | 175/304頁(yè) |
| 文件大?。?/td> | 2092K |
| 代理商： | AM79C975 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)當(dāng)前第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)
Am79C973/Am79C975
175
P R E L I M I N A R Y
and is not affected by S_RESET
or STOP.
4-3
PHYSEL[1:0]
PHYSEL[1:0] bits allow for soft-
ware controlled selection of differ-
ent operation and test modes.
The normal mode of operation is
when both bits 0 and 1 are set to
0 to select the Expansion ROM/
Flash. Setting bit 0 to 1 and bit 1
to 0 allows snooping of the inter-
nal MII-compatible bus to allow
External Address Detection Inter-
face
(EADI).
SEL[1:0] = 10 enables the
external MII mode. Since the in-
ternal 10/100 PHY is disabled in
this
mode,
the
Am79C975 controller behaves
like an Am79C972 PCnet-
FAST
+
device. Tehese controllers are
not designed to support two
PHYs at a time as only one PHY
can be used at a given time. An
external or internal PHY can be
used by reconfiguring the EE-
PROM or the BCI18 register. See
the following table for details.
Setting
PHY-
Am79C973/
Read accessible always, these
bits can only be written from the
EEPROM unless a write-enable
bit BCR2[13], is set. PHYSEL
[1:0] is cleared by H_RESET and
is not affected by S_RESET or
STOP.
2-0
LINBC
Reserved locations. Read acces-
sible always; write accessible
only when either the STOP or the
SPND bit is set. After H_RESET,
the value in these bits will be
001b. The setting of these bits
have
no
effect
Am79C973/Am79C975 controller
function. LINBC is not affected by
S_RESET or STOP.
on
any
BCR19: EEPROM Control and Status
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
PVALID
EEPROM Valid status bit. Read
accessible only. PVALID is read
only; write operations have no ef-
fect. A value of 1 in this bit indi-
cates that a PREAD operation
has occurred, and that (1) there is
an EEPROM connected to the
Am79C973/Am79C975 controller
interface pins and (2) the con-
tents read from the EEPROM
have passed the checksum verifi-
cation operation.
A value of 0 in this bit indicates a
failure in reading the EEPROM.
The checksum for the entire 82
bytes of EEPROM is incorrect or
no EEPROM is connected to the
interface pins.
PVALID is set to 0 during
H_RESET and is unaffected by
S_RESET or the STOP bit. How-
ever, following the H_RESET op-
eration, an automatic read of the
EEPROM will be performed. Just
as is true for the normal PREAD
command, at the end of this auto-
matic read operation, the PVALID
bit may be set to 1. Therefore,
H_RESET will set the PVALID bit
to 0 at first, but the automatic EE-
PROM read operation may later
set PVALID to a 1.
If PVALID becomes 0 following
an EEPROM read operation (ei-
ther automatically generated af-
ter H_RESET, or requested
through PREAD), then all EE-
PROM-programmable BCR loca-
tions will be reset to their
H_RESET values. The content of
the Address PROM locations,
however, will not be cleared.
If no EEPROM is present at the
EESK, EEDI, and EEDO pins,
then all attempted PREAD com-
mands will terminate early and
PVALID will
not
be set. This ap-
plies to the automatic read of the
PHYSEL [1:0]
Mode
00
Expansion ROM/Flash - Normal Mode
01
EADI/Internal MII Snoop Mode
10
Full MII Mode - An External PHY
Required
11
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C973 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C975BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\W | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975BKDW | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。