參數(shù)資料
型號(hào)： AM79C90PCTR
廠商： Advanced Micro Devices, Inc.
英文描述： CMOS Local Area Network Controller for Ethernet (C-LANCE)
中文描述： 的CMOS局域網(wǎng)控制器（丙應(yīng)聘以太網(wǎng)）
文件頁(yè)數(shù)： 23/62頁(yè)
文件大小： 437K
代理商： AM79C90PCTR
P R E L I M I N A R Y
AMD
23
Am79C90
Control and Status Register 3 (CSR3)
CSR3 allows redefinition of the Bus Master interface.
READ/WRITE:
Accessible only when the STOP bit
of CSR
0
is ONE and RAP = 11.
CSR
3
is cleared by
RESET
or by
setting the STOP bit in CSR
0
.
3
15
0
2 1
BCON
ACON
BSWP
RES
17881B-18
Bit
Name
Description
15:03
RES
Reserved. Read as zeroes. Write as
zeroes.
BYTE SWAP allows the chip to oper-
ate in systems that consider bits
(15:08) of data to be pointed at an
even address and bits (07:00) to be
pointed at an odd address.
When BSWP = 1, the C-LANCE will
swap the high and low bytes on DMA
data transfers between the Receive
FIFO and bus memory. Only data
from the Receive FIFO transfers is
swapped; the Initialization Block
data and the Descriptor Ring entries
are NOT swapped.
BSWP is READ/WRITE and cleared
by
RESET
or by setting the STOP bit
in CSR
0
.
ALE CONTROL defines the asser-
tive state of ALE when the C-LANCE
is a Bus Master. ACON is READ/
WRITE and cleared by
RESET
and
by setting the STOP bit in CSR
0
.
ACON
0
Asserted HIGH
1
BYTE CONTROL redefines the Byte
Mask and Hold l/O pins. BCON is
READ/WRITE
and
RESET
or by setting the STOP bit in
CSR
0
.
BCON
Pin 16 Pin 15 Pin 17
BM
1
1
BUSAKO
BYTE
BUSRQ
02
BSWP
01
ACON
ALE
Asserted LOW
00
BCON
cleared
by
0
BM
0
HOLD
All data transfers from the C-LANCE in the Bus Master
mode are in words. However, the C-LANCE can handle
odd address boundaries and/or packets with an odd
number of bytes.
Initialization
Initialization Block
Chip initialization includes the reading of the initializa-
tion block in memory to obtain the operating parame-
ters. The following is a definition of the Initialization
Block.
The Initialization Block is read by the C-LANCE when
the INIT bit in CSR0 is set. The INIT bit should be set be-
fore or concurrent with the STRT bit to insure proper pa-
rameter initialization and chip operation. After the
C-LANCE has read the Initialization Block, IDON is set
in CSR0 and an interrupt is generated if INEA = 1.
Higher Address
TLEN–TDR (23:16)
TDRA (15:00)
RLEN–RDRA (23:16) IADR +18
RDRA (15:00)
LADRF (63:48)
LADRF (47:32)
LADRF (31:16)
LADRF (15:00)
PADR (47:32)
PADR (31:16)
PADR (15:00)
IADR +22
IADR +20
IADR +16
IADR +14
IADR +12
IADR +10
IADR +08
IADR +06
IADR +04
IADR +02
IADR +00
Base Address of Block MODE
Mode
The Mode Register allows alteration of the C-LANCE’s
operating parameters. Normal operation is with the
Mode Register clear.
DRX
DTX
LOOP
DTCR
COLL
DRTY
INTL
EMBA
15
0
2 1
3
4
6 5
7
RES
PROM
14
17881B-19
8
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