參數(shù)資料
型號(hào)： AM79C90PCTR
廠商： Advanced Micro Devices, Inc.
英文描述： CMOS Local Area Network Controller for Ethernet (C-LANCE)
中文描述： 的CMOS局域網(wǎng)控制器（丙應(yīng)聘以太網(wǎng)）
文件頁數(shù)： 20/62頁
文件大?。?/td> 437K
代理商： AM79C90PCTR
AMD
P R E L I M I N A R Y
20
Am79C90
Register Address Port (RAP)
RES
17881B-14
CSR 1:0
Bit
Name
Description
15:02
RES
Reserved. Read as zeroes. Write as
zeroes.
CSR address select. READ/WRITE.
Selects the CSR to be accessed
through the RDP. RAP is cleared by
Bus
RESET
.
CSR(1 :0)
01:00
CSR(1:0)
CSR
CSR
0
CSR
1
CSR
2
CSR
3
00
01
10
11
Control and Status Register Definition
Control and Status Register 0 (CSR0)
ERR
BABL
CERR
MISS
MERR
RINT
TINT
IDON
INIT
STRT
STOP
TDMD
TXON
RXON
INEA
INTR
The C-LANCE updates CSR
0
by logical “ORing” the pre-
vious and present value of CSR
0.
17881B-15
15
0
Bit
Name
Description
15
ERR
ERROR summary is set by the
“ORing” of BABL, CERR, MISS and
MERR. ERR remains set as long as
any of the error flags are true.
ERR is read only; writing it has no ef-
fect. It is cleared by Bus
RESET
, set-
ting the STOP bit, or clearing the
individual error flags.
Bit
Name
Description
14
BABL
BABBLE is a transmitter timeout er-
ror. It indicates that the transmitter
has been on the channel longer than
the time required to send the maxi-
mum length packet.
BABL is a flag which indicates ex-
cessive length in the transmit buffer.
It will be set after 1519 bytes have
been transmitted, excluding pream-
ble and start frame delimiter; the
C-LANCE will continue to transmit
until the whole packet is transmitted
or until there is a failure before the
whole packet is transmitted. When
BABL error occurs, an interrupt will
be generated if INEA = 1.
BABL is READ/CLEAR ONLY and is
set by the C-LANCE, and cleared by
writing a “1” into the bit. Writing a ”0”
has no effect. It is cleared by
RESET
or by setting the STOP bit.
COLLISION ERROR indicates that
the collision input to the C-LANCE
was not asserted during the trans-
mission, nor within 4.0
μ
s after the
transmit completed. The collision af-
ter transmission is a transceiver test
feature. This function is also known
as heartbeat or SQE (Signal Quality
Error) test.
CERR is READ/CLEAR ONLY and
is set by the C-LANCE and cleared
by writing a “1” into the bit. Writing a
“0” has no effect. It is cleared by
RE-
SET
or by setting the STOP bit.
CERR error will not cause an inter-
rupt to occur (INTR = 0).
MISSED PACKET is set when the
receiver loses a packet because it
does not own any receive buffer, in-
dicating loss of data.
FIFO overflow is not reported be-
cause there is no receive ring entry
in which to write status.
When MISS is set, an interrupt will
be generated if INEA = 1.
MISS is READ/CLEAR ONLY, and is
set by the C-LANCE and cleared by
writing a “1” into the bit. Writing a “0”
has no effect. It is cleared by
RESET
or by setting the STOP bit.
13
CERR
12
MISS
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