參數(shù)資料
型號(hào)： AM79C90PCTR
廠(chǎng)商： Advanced Micro Devices, Inc.
英文描述： CMOS Local Area Network Controller for Ethernet (C-LANCE)
中文描述： 的CMOS局域網(wǎng)控制器（丙應(yīng)聘以太網(wǎng)）
文件頁(yè)數(shù)： 21/62頁(yè)
文件大?。?/td> 437K
代理商： AM79C90PCTR
P R E L I M I N A R Y
AMD
21
Am79C90
Bit
Name
Description
11
MERR
MEMORY ERROR is set when the
C-LANCE is the Bus Master and has
not received
READY
within 25.6
μ
s
after asserting the address on the
DAL lines.
When a Memory Error is detected,
the receiver and transmitter are
turned off (CSR
0
, TXON = 0, RXON
= 0) and an interrupt is generated if
INEA = 1.
MERR is READ/CLEAR ONLY, and
is set by the C-LANCE and cleared
by writing a “1” into the bit. Writing a
“0” has no effect. It is cleared by
RESET
or by setting the STOP bit.
RECEIVER INTERRUPT is set
when the C-LANCE updates an en-
try in the Receive Descriptor Ring for
the last buffer received or reception
is stopped due to a failure.
When RINT is set, an interrupt is
generated if INEA = 1.
RINT is READ/CLEAR ONLY, and is
set by the C-LANCE and cleared by
writing a “1” into the bit. Writing a “0”
has no effect. It is cleared by
RESET
or by setting the STOP bit.
TRANSMITTER INTERRUPT is set
when the C-LANCE updates an en-
try in the transmit descriptor ring for
the last buffer sent or transmission is
stopped due to a failure.
When TINT is set, an interrupt is
generated if INEA = 1.
TINT is READ/CLEAR ONLY and is
set by the C-LANCE and cleared by
writing a “1” into the bit. Writing a “0”
has no effect. It is cleared by
RESET
or by setting the STOP bit.
INITIALIZATION DONE indicates
that the C-LANCE has completed
the initialization procedure started
by setting the INIT bit. When IDON is
set, the C-LANCE has read the In-
itialization Block from memory and
stored the new parameters.
When IDON is set, an interrupt is
generated if INEA = 1.
10
RINT
09
TINT
08
IDON
IDON is READ/CLEAR ONLY, and is
set by the C-LANCE and cleared by
writing a “1” into the bit. Writing a “0”
has no effect. It is cleared by
RESET
or by setting the STOP bit.
Bit
Name
Description
07
INTR
INTERRUPT FLAG is set by the
“ORing” of BABL, MISS, MERR,
RINT, TINT and IDON. If INEA = 1
and INTR = 1, the
INTR
pin will be
LOW.
INTR is READ ONLY; writing this bit
has no effect. INTR is cleared by
RESET, by setting the STOP bit, or
by clearing the condition causing the
interrupt.
INTERRUPT ENABLE allows the
INTR
pin to be driven LOW when the
Interrupt Flag is set. If INEA = 1 and
INTR = 1, the
INTR
pin will be Low. If
INEA = 0, the
INTR
pin will be HIGH,
regardless of the state of the Inter-
rupt Flag.
INEA is READ/WRITE and cleared
by RESET or by setting the STOP
bit.
INEA can be set at any time, regard-
less of the state of the STOP bit.
(reference Appendix B).
RECEIVER ON indicates that the re-
ceiver is enabled. RXON is set when
STRT is set if DRX = 0 in the MODE
register in the initialization block and
the initialization block has been read
by the C-LANCE by setting the INIT
bit. RXON is cleared when IDON is
set from setting the INIT bit and DRX
= 1 in the MODE register, or a mem-
ory error (MERR) has occurred.
RXON is READ ONLY; writing this
bit has no effect. RXON is cleared by
RESET
or by setting the STOP bit.
TRANSMITTER ON indicates that
the transmitter is enabled. TXON is
set when STRT is set if DTX = 0 in
the MODE register in the initializa-
tion block and the INIT bit has been
set. TXON is cleared when IDON is
set and DTX = 1 in the MODE regis-
ter, or an error, such as MERR,
UFLO or BUFF, has occurred during
transmission.
TXON is READ ONLY; writing this bit
has no effect. TXON is cleared by
RESET
or by setting the STOP bit.
06
INEA
05
RXON
04
TXON
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