參數(shù)資料
型號： AM70PDL127CDH
廠商： Advanced Micro Devices, Inc.
英文描述： 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
中文描述： 2 × 64兆位（8米× 16位）的CMOS 3.0伏特，只有頁面模式閃存數(shù)據(jù)存儲128兆位（8米× 16位）的CMOS
文件頁數(shù)： 77/127頁
文件大?。?/td> 849K
代理商： AM70PDL127CDH
November 24, 2003
Am70PDL127CDH/Am70PDL129CDH
75
A D V A N C E I N F O R M A T I O N
PSRAM AC CHARACTERISTICS
Figure 25.
Standby Mode State Machines
Standby Mode Characteristic
AC Characteristics
(V
CC
= 2.7-3.1 V, TA= -40 to 85
°
C)
t
WP
(min)= 70 ns for continuous write operation over 50 times.
CS2s =V
IL
CS#1s=V
IH
CS2s=V
IH
CS#1=V
IL
, UB or/and LB=V
IL
CS2s=V
IH
Power On
Initial State
(Wait 200
μ
s)
Active
Standby
Mode
Deep Power
Down Mode
CS#1s=V
IH
and CS2s=V
IH
CS2s =V
IL
CS#1s=V
IH
,
CS2s=V
IH
Power Mode
Standby
Deep Power Down
Memory Cell Data
Valid
Invalid
Standby Current (
μ
A)
80
20
Wait Time (
μ
s)
0
200
Parameter List
Symbol
Speed Bins
66/85 ns
Min
70
-
-
-
-
10
10
5
0
0
0
5
70
60
0
60
60
55
(Note 1)
0
0
30
0
5
Units
Max
-
70
70
35
70
-
-
-
25
25
25
-
-
-
-
-
-
Read
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
UB#, LB# Access Time
Chip Select to Low-Z Output
UB#, LB# Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB#, LB# Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
UB#, LB# Valid to End of Write
t
RC
t
AA
t
CO
t
OE
t
BA
t
LZ
t
BLZ
t
OLZ
t
HZ
t
BHZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
BW
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write
Write Pulse Width
t
WP
-
ns
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
t
WR
t
WHZ
t
DW
t
DH
t
OW
-
ns
ns
ns
ns
ns
25
-
-
-
相關(guān)PDF資料
PDF描述
Am70PDL127CDH66IS 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
Am70PDL127CDH66IT 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
Am70PDL127CDH85IS 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
Am70PDL127CDH85IT 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
Am70PDL129CDH 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM70PDL127CDH66I 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
AM70PDL127CDH66IS 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
AM70PDL127CDH66IT 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
AM70PDL127CDH85I 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
AM70PDL127CDH85IS 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
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