參數(shù)資料
型號: AM50DL128CH
英文描述: Am50DL128CH - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述: Am50DL128CH -堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁數(shù): 56/70頁
文件大?。?/td> 1042K
代理商: AM50DL128CH
May 19, 2003
Am50DL9608G
55
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
OE#
WE#
Addresses
t
OEH
t
DH
t
AHT
t
ASO
t
OEPH
t
OE
Valid Data
(first read)
(second read)
(stops toggling)
t
CEPH
t
AHT
t
AS
DQ6/DQ2
Valid Data
Valid
Status
Valid
Status
Valid
Status
RY/BY#
CE#f
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 23.
Toggle Bit Timings (During Embedded Algorithms)
Note:
DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to
toggle DQ2 and DQ6.
Figure 24.
DQ2 vs. DQ6
Enter
Erase
Erase
Resume
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
Suspend
Program
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Embedded
Erasing
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