參數(shù)資料
型號(hào): AM50DL128CH
英文描述: Am50DL128CH - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述: Am50DL128CH -堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁(yè)數(shù): 30/70頁(yè)
文件大?。?/td> 1042K
代理商: AM50DL128CH
May 19, 2003
Am50DL9608G
29
P R E L I M I N A R Y
Table 16.
Am29DL640G Device Geometry Definition
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Description
27h
4Eh
0017h
Device Size = 2
N
byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of byte in multi-byte write = 2
N
(00h = not supported)
2Ch
58h
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
007Dh
0000h
0000h
0001h
Erase Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0007h
0000h
0020h
0000h
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
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AM50DL128CH70IT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:STACKED MULTI-CHIP PACKAGE (MCP) FLASH MEMORY AND SRAM